SPRUGZ8D Datasheet, PDF (147/3016 Pages) Texas Instruments – Technical Reference Manual

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Media Controller Subsystem
Table 1-18. Counter Timer STM Master ID Register (CACHE_SCTM_CTSTMMSTID) Field
Descriptions (continued)
Bits
6:0 MASTID
Field Name
Description
HW Master ID for this module.
Type
RW
Reset
0
1.2.7.12 Counter Timer STM Interval Register (CACHE_SCTM_CTSTMINTVL)
The Counter Timer STM Interval Register (CACHE_SCTM_CTSTMINTVL) is described in Table 1-19.
Table 1-19. Counter Timer STM Interval Register (CACHE_SCTM_CTSTMINTVL) Field Descriptions
Bits
31:16
15:0
Reserved
INTERVAL
Field Name
Description
Reserved
Periodic export interval
Type
R
RW
Reset
0
0
1.2.7.13 Counter Timer STM Count Select Register 0(CACHE_SCTM_CTSTMSEL0)
The Counter Timer STM Count Select Register 0(CACHE_SCTM_CTSTMSEL0) is described in Table 1-
20.
Table 1-20. Counter Timer STM Count Select Register 0(CACHE_SCTM_CTSTMSEL0) Field
Descriptions
Bits
Field Name
31:0 COUNTSEL
Description
The counter selection bit-field
Type
RW
Reset
0
1.2.7.14 Counter Timer Interval Number Debug Event Register (CACHE_SCTM_TINTVL_R_i)
The Counter Timer Interval Number Debug Event Register (CACHE_SCTM_TINTVL_R_i) is described in
Table 1-21.
Table 1-21. Counter Timer Interval Number Debug Event Register (CACHE_SCTM_TINTVL_R_i)
Field Descriptions
Bits
31:0 INTERVAL
Field Name
Description
Interval match value for the timers in the
SCTM
Type
RW
Reset
0
1.2.7.15 Counter Timer Number Debug Event Register (CACHE_SCTM_CTDBGNUM)
The Counter Timer Number Debug Event Register (CACHE_SCTM_CTDBGNUM) is described in Table 1-
22.
Table 1-22. Counter Timer Number Debug Event Register (CACHE_SCTM_CTDBGNUM) Field
Descriptions
Bits
31:3 Reserved
2:0 NUMEVT
Field Name
Description
Reserved
Number of input selectors for debug events
Type
R
R
Reset
0
0
1.2.7.16 Counter Timer Global Enable Register 0(CACHE_SCTM_CTGNBL0)
The Counter Timer Global Enable Register 0(CACHE_SCTM_CTGNBL0) is described in Table 1-23.
SPRUGZ8D – 14 November 2011 – Revised April 2013
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