SPRUGZ8D Datasheet, PDF (1460/3016 Pages) Texas Instruments – Technical Reference Manual

CPSW Architecture
Figure 9-10. RMII Interface Connections
RMII_TXD[1–0]
RMII_TXEN
RMREFCLK
RMII_RXD[1–0]
RMII_CRS_DV
RMII_RXER
MDIO_CLK
MDIO_D
Physlcal
Layer
Device
(PHT)
50 MHz
Transformer
RJ-45
www.ti.com
Signal
RMTXD (1-0)
RMXEN
RMREFCLK
RMRXD (1-0)
RMCRSDV
R,RXER
MDCLK
MDIO
Type
O
O
I/O
I
I
I
O
I/O
Table 9-17. RMII Signal Descriptions
Description
Transmit data (RMII_TXD). The transmit data pins are a collection of 2 bits of data. RMTDX0 is the
least-significant bit (LSB). The signals are synchronized by RMREFCLK and valid only when
RMTXEN is asserted.
Transmit enable (RMII_TXEN). The transmit enable signal indicates that the RMII_TXD pins are
generating data for use by the PHY. RMII_TXEN is synchronous to RMREFCLK.
RMII reference clock. (RMREFCLK).
The reference clock is used to synchronize all RMII signals. RMREFCLK must be continuous and
fixed at 50 MHz.
Receive data (RMII_RXD). The receive data pins are a collection of 2 bits of data. RMRDX0 is the
least-significant bit (LSB). The signals are synchronized by RMREFCLK and valid only when
RMCRSDV is asserted and RMRXER is de-asserted.
Carrier sense/receive data valid (RMCRSDV). Multiplexed signal between carrier sense and receive
data valid.
Receive error (RMII_RXER). The receive error signal is asserted to indicate that an error was
detected in the received frame.
Management data clock (MDIO_CLK). The MDIO data clock is sourced by the MDIO module on the
system. It is used to synchronize MDIO data access operations done on the MDIO pin.
MDIO DATA(MDI0_D). MDIO data pin drives PHY management data into and out of the PHY by way
of an access frame consisting of start of frame, read/write indication, PHY address, register address,
and data bit cycles. The MDIO_D pin acts as an output for all but the data bit cycles at which time it
is an input for read operations.
9.2.1.7.3 RGMII Interface
The CPRGMII peripheral shall be compliant to the RGMII specification document.
9.2.1.7.3.1 Features
• Supports 1000/100/10 Mbps Speed
• MII mode is not supported
• Selectable internal delay on transmit
9.2.1.7.3.2 RGMII Receive (RX)
The CPRGMII receive (RX) interface converts the source synchronous DDR input data from the external
RGMII PHY into the required G/MII (CPGMAC) signals.
1460
3PSW Ethernet Subsystem (EMAC)
SPRUGZ8D – 14 November 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated
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