SPRUGZ8D Datasheet, PDF (2543/3016 Pages) Texas Instruments – Technical Reference Manual

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Registers (Controller and PHY)
21.4.22 Port Interrupt Enable Register (P0IE)
The port interrupt enable register (P0IE) enables and disables the reporting of the corresponding interrupt
to system software. When a bit is set (1), and the corresponding interrupt condition is active, then the
SATASS intrq output is asserted. Interrupt sources that are disabled (0) are still reflected in the status
registers. This register is symmetrical with the P0IS register. This register is reset on Global reset.
The P0IE register is shown in Figure 21-23 and described in Table 21-24.
Figure 21-23. Port Interrupt Enable Register (P0IE)
31
30
29
28
27
26
25
24
23
22
21
16
Rsvd TFEE HBFE HBDE IFE INFE Rsvd OFE IPME PRCE
Reserved
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0
R-0
15
8
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
7
DMPE
R/W-0
6
PCE
R/W-0
5
DPE
R/W-0
4
UFE
R/W-0
3
SDBE
R/W-0
2
DSE
R/W-0
1
PSE
R/W-0
0
DHRE
R/W-0
Bit Field
31 Reserved
30 TFEE
29 HBFE
28 HBDE
27 IFE
26 INFE
25 Reserved
24 OFE
23 IPME
22 PRCE
21-8 Reserved
7 DMPE
6 PCE
5 DPE
4 UFE
3 SDBE
2 DSE
1 PSE
0 DHRE
Table 21-24. Port Interrupt Enable Register (P0IE) Field Descriptions
Value
0
0-1
0-1
0-1
0-1
0-1
0
0-1
0-1
0-1
0
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
Description
Reserved. No CPD capability exist since CPD related pins are not bonded out for the device. If need
this feature, use of GPIO is recommended.
Task File Error Enable. When set to 1, GHC.IE = 1, and P0IS.HBFS = 1, the intrq output is asserted.
Host Bus Fatal Error Enable. When set to 1, GHC.IE = 1, and P0IS.HBFS = 1, the interq output is
asserted.
Host Bus Data Error Enable. When set to 1, GHC.IE = 1, and P0IS.HBDS = 1, the intrq output is
asserted.
Interface Fatal Error Enable. When set to 1, GHC.IE = 1, and P0IS.IFS = 1, the intrq output is asserted.
Interface Non-fatal Error Enable. When set to 1, GHC.IE = 1, and P0IS.INFS = 1, the intrq output is
asserted.
Reserved.
Overflow Enable. When set to 1, GHC.IE = 1, and P0IS.OFS = 1, the intrq output is asserted.
Incorrect Port Multiplier Enable. When set to 1, GHC.IE = 1, and P0IS.IPMS = 1, the intrq output is
asserted.
PHY Ready Change Enable. When set to 1, GHC.IE = 1, and P0IS.PRCS = 1, the intrq output is
asserted.
Reserved.
Device Mechanical Presence Enable. When set to 1, GHC.IE = 1, and P0IS.DMPS = 1, the intrq output
is asserted.
Port Change Interrupt Enable. When set to 1, GHC.IE = 1, and P0IS.PCS = 1, the intrq output is
asserted.
Descriptor Processed Interrupt Enable. When set to 1, GHC.IE = 1 and P0IS.DPS = 1, the intrq output
is asserted.
Unknown FIS Interrupt Enable. When set to 1, GHC.IE = 1, and P0IS.UFS = 1, the intrq output is
asserted.
Set Device Bits FIS Interrupt Enable. When set to 1, GHC.IE = 1, and P0IS.SDBS = 1, the intrq output
is asserted.
DMA Setup FIS Interrupt Enable. When set to 1, GHC.IE = 1, and P0IS.PSS = 1, the intrq output is
asserted.
PIO Setup FIS Interrupt Enable. When set to 1, GHC.IE = 1, and P0IS.PSS = 1, the intrq output is
asserted.
Device Host Register FIS Interrupt Enable. When set to 1, GHC.IE = 1, and P0IS.DHRS = 1, the intrq
output is asserted.
SPRUGZ8D – 14 November 2011 – Revised April 2013
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