SPRUGZ8D Datasheet, PDF (515/3016 Pages) Texas Instruments – Technical Reference Manual

www.ti.com
2.10.1.13 MPUPLL_FRACCTRL Register (offset = 68h) [reset = 0h]
MPUPLL_FRACCTRL is shown in Figure 2-39 and described in Table 2-55.
Controlls the fractional portion of Modena PLL
PRCM Registers
Figure 2-39. MPUPLL_FRACCTRL Register
31
30
29
28
27
26
25
24
DOWNSPREAD
ModFreqDividerExponent
ModFreqDividerMantissa
R/W-0h
R/W-0h
R/W-0h
23
22
21
ModFreqDividerMantissa
R/W-0h
20
Reserved
R-0h
19
18
DeltaMStepInteger
R/W-0h
17
16
DeltaMStepFraction
R/W-0h
15
14
13
12
11
10
9
8
DeltaMStepFraction
R/W-0h
7
6
5
4
3
2
1
0
DeltaMStepFraction
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Bit
31
30-28
27-21
20
19-18
17-0
Table 2-55. MPUPLL_FRACCTRL Register Field Descriptions
Field
DOWNSPREAD
Type
R/W
ModFreqDividerExponent R/W
ModFreqDividerMantissa R/W
Reserved
R
DeltaMStepInteger
R/W
DeltaMStepFraction
R/W
Reset
0h
0h
0h
0h
0h
0h
Description
Controls frequency spread
0x0 : enables both side frequency spread about the programmed
frequency.
0x1 : enables low frequency spread only
Exponent of the REFCLK divider to define the modulation frequency.
Mantissa of the REFCLK divider to define the modulation frequency
Integer part of Frequency Spread control.
The fraction part of Frequency Spread control
SPRUGZ8D – 14 November 2011 – Revised April 2013
Power, Reset, and Clock Management (PRCM) Module 515
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated