SPRUGZ8D Datasheet, PDF (524/3016 Pages) Texas Instruments – Technical Reference Manual

PRCM Registers
2.10.1.20 DSPPLL_TENABLEDIV Register (offset = 8Ch) [reset = 0h]
DSPPLL_TENABLEDIV is shown in Figure 2-46 and described in Table 2-62.
The PLL TENABLEDIV register is used to load the M2,N2 dividers of respective PLL
Figure 2-46. DSPPLL_TENABLEDIV Register
31
30
29
28
27
26
25
Reserved
R-0h
23
22
21
20
19
18
17
Reserved
R-0h
15
14
13
12
11
10
9
Reserved
R-0h
7
6
5
4
3
2
1
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 2-62. DSPPLL_TENABLEDIV Register Field Descriptions
Bit
31-1
0
Field
Reserved
TENABLEDIV
Type
R
R/W
Reset
0h
0h
Description
M2 and N2 latch (active rise edge)
www.ti.com
24
16
8
0
TENABLEDIV
R/W-0h
524 Power, Reset, and Clock Management (PRCM) Module
SPRUGZ8D – 14 November 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated
Submit Documentation Feedback