SPRUGZ8D Datasheet, PDF (1566/3016 Pages) Texas Instruments – Technical Reference Manual

Registers
www.ti.com
9.4.1.105 CPGMAC_SL1 RX Packet Priority to Header Priority Mapping Register (SL1_RX_PRI_MAP)
(0x724)
31
Rsvd
R-0
Figure 9-125. CPGMAC_SL1 RX Packet Priority to Header Priority Mapping Register
(SL1_RX_Pri_Map)
30
28
27
26
24
23
22
20
19
18
16
PRI7
Rsvd
PRI6
Rsvd
PRI5
Rsvd
PRI4
R/W-7h
R-0
R/W-6h
R-0
R/W-5h
R-0
R/W-4h
15
14
12
11
10
8
Rsvd
PRI3
Rsvd
PRI2
R-0
R/W-3h
R-0
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
7
Rsvd
R-0
6
4
PRI1
R/W-1h
3
Rsvd
R-0
2
0
PRI0
R/W-0h
Table 9-129. CPGMAC_SL1 RX Packet Priority to Header Priority Mapping Register (SL1_Pri_Map)
Field Descriptions
Bit
31
30-28
27
26-24
23
22-20
19
18-16
15
14-12
11
10-8
7
6-4
3
2-0
Field
Reserved
PRI7
Reserved
PRI6
Reserved
PRI5
Reserved
PRI4
Reserved
PRI3
Reserved
PRI2
Reserved
PRI1
Reserved
PRI0
Value
0
0-7h
0
0-7h
0
0-7h
0
0-7h
0
0-7h
0
0-7h
0
0-7h
0
0-7h
Description
Reserved. Read as zero
Priority 7. A packet priority of 7 is mapped (changed) to this value.
Reserved. Read as zero
Priority 6. A packet priority of 6 is mapped (changed) to this value.
Reserved. Read as zero
Priority 5. A packet priority of 5 is mapped (changed) to this value.
Reserved. Read as zero
Priority 4. A packet priority of 4 is mapped (changed) to this value.
Reserved. Read as zero
Priority 3. A packet priority of 3 is mapped (changed) to this value.
Reserved. Read as zero
Priority 2. A packet priority of 2 is mapped (changed) to this value.
Reserved. Read as zero
Priority 1. A packet priority of 1 is mapped (changed) to this value.
Reserved. Read as zero
Priority 0. A packet priority of 0 is mapped (changed) to this value.
1566
3PSW Ethernet Subsystem (EMAC)
SPRUGZ8D – 14 November 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated
Submit Documentation Feedback