SPRUGZ8D Datasheet, PDF(1091/3016 Page) Texas Instruments – Technical Reference Manual

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SPRUGZ8D Datasheet, PDF (1091/3016 Pages) Texas Instruments – Technical Reference Manual

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Registers

5.14.1 DCAN Control Registers

After hardware reset, the registers of the DCAN hold the values shown in the register descriptions.

Additionally, the Bus-Off state is reset and the CAN_TX pin is set to recessive (HIGH). The Init bit in the

CAN control register is set to enable the software initialization. The DCAN will not influence the CAN bus

until the CPU resets Init to '0'.

Table 5-10. DCAN Control Register Summary Table

Offset

0x00

0x04

0x08

0x0C

0x10

0x14

0x1C

0x80

0x84

0x88 to

0x94

0x98

0x9C to

0xA8

0xAC

0xB0 to

0xBC

0xC0

0xC4 to

0xD0

0xD8 to

0xE4

0x100

0x120

0x104

0x124

0x108

0x128

0x10C

0x12C

0x110

0x114

0x130

0x134

0x140

0x144

0x148

0x14C

0x150

0x154

0x160 to

0x16C

0x1E0

Acronym

DCAN CTL

DCAN ES and

PARITYERR_EOI

DCAN ERRC

DCAN BTR

DCAN INT

DCAN TEST

DCAN PERR

DCAN ABOTR

DCAN TXRQ X

DCAN TXRQ12 to

DCAN TXRQ78

DCAN NWDAT X

DCAN NWDAT12 to

DCAN NWDAT78

DCAN INTPND X

DCAN INTPND12 to

DCAN INTPND78)

DCAN MSGVAL X

DCAN MSGVAL12 to

DCAN MSGVAL78

DCAN INTMUX12 to

DCAN INTMUX78

DCAN IF1CMD

DCAN IF2CMD

DCAN IF1MSK

DCAN IF2MSK

DCAN IF1ARB

DCAN IF2ARB

DCAN IF1MCTL

DCAN IF2MCTL

DCAN IF1DATA

DCAN IF1DATB

DCAN IF2DATA

DCAN IF2DATB

DCAN IF3OBS

DCAN IF3MSK

DCAN IF3ARB

DCAN IF3MCTL

DCAN IF3DATA

DCAN IF3DATB

DCAN IF3UPD12 to

IF3UPD78

DCAN TIOC

Description

CAN Control Register

Error and Status Register

Parity Error EOI Register

Error Counter Register

Bit Timing Register

Interrupt Register

Test Register

Parity Error Code Register

Auto-Bus-On Time Register

Transmission Request X Register

Transmission Request Registers

New Data X Register

New Data Registers

Interrupt Pending X Register

Interrupt Pending Registers

Message Valid X Register

Message Valid Registers

Interrupt Multiplexer Registers

IF1 Command Registers

IF2 Command Registers

IF1 Mask Register

IF2 Mask Register

IF1 Arbitration Register

IF2 Arbitration Register

IF1 Message Control Register

IF2 Message Control Register

IF1 Data A Register

IF1 Data B Register

IF2 Data A Register

IF2 Data B Register

IF3 Observation Register

IF3 Mask Register

IF3 Arbitration Register

IF3 Message Control Register

IF3 Data A Register

IF3 Data B Register

IF3 Update Enable Registers

CAN TX IO Control Register

Section

Section 5.14.1.1

Section 5.14.1.2

Section 5.14.1.3

Section 5.14.1.4

Section 5.14.1.5

Section 5.14.1.6

Section 5.14.1.7

Section 5.14.1.8

Section 5.14.1.9

Section 5.14.1.10

Section 5.14.1.11

Section 5.14.1.12

Section 5.14.1.13

Section 5.14.1.14

Section 5.14.1.15

Section 5.14.1.16

Section 5.14.1.17

Section 5.14.1.18

Section 5.14.1.18

Section 5.14.1.19

Section 5.14.1.19

Section 5.14.1.20

Section 5.14.1.20

Section 5.14.1.21

Section 5.14.1.21

Section 5.14.1.22

Section 5.14.1.22

Section 5.14.1.22

Section 5.14.1.22

Section 5.14.1.23

Section 5.14.1.24

Section 5.14.1.25

Section 5.14.1.26

Section 5.14.1.27

Section 5.14.1.27

Section 5.14.1.28

Section 5.14.1.29

SPRUGZ8D â 14 November 2011 â Revised April 2013

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DCAN Controller Area Network1091

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