SPRUGZ8D Datasheet, PDF (839/3016 Pages) Texas Instruments – Technical Reference Manual

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CONTROL_MODULE Registers
Offset
6A0h
6A4h
6A8h
6B0h
6B4h
6D8h
6DCh
6E0h
6E4h
6E8h
6ECh
6F0h
6F4h
720h
724h
728h
72Ch
730h
734h
738h
73Ch
740h
770h
774h
778h
77Ch
Table 3-3. CONTROL_MODULE REGISTERS (continued)
Acronym
Register Name
SMRT_CTRL
The SMRT_CTRL Register reflects the control for the
srsleep signal for the SRs .
ARM_CORTEX_A8_HW_DBG_SE This register controls what kind of debug info is returned
L
by ARM Cortex-A8.
ARM_CORTEX_A8_HW_DBG_INF This register shows the debug info bus from ARM
O
Cortex-A8. Please see below for definition. The selection
bits are HW_DBG_SEL (3:0) in the MMR
ARM_CORTEX_A8_HW_DBG_SEL
PRCM_DEBUG_ALWON_DEFAUL This register is for PRCM debug.
T
PRCM_DEBUG_PD_DOMAIN_ST This register is for PRCM debug.
ATUS
PCIE_PLLCFG0
This is connected to "CF_APLL_0" on SERDES ANA
Initial Settings required prior to power up sequence:
PCIE_100M: 4000 7000 ; SATA_20M: C000 7060 ;
SATA_100M: 4000 7060
PCIE_PLLCFG1
This is connected to "CF_APLL_1" on SERDES ANA
Initial Settings required prior to power up sequence:
PCIE_100M: 0064 0000 ; SATA_100MHz: 912C 0000 ;
SATA_20MHz: C02C 0000
PCIE_PLLCFG2
This is connected to "CF_APLL_2" on SERDES ANA
Initial Settings required prior to power up sequence:
PCIE: 0000 0000 -- SATA: 0000 0000 (both modes)
PCIE_PLLCFG3
This is connected to "CF_APLL_3" on SERDES ANA
Initial Settings required prior to power up sequence:
0040 08E0
PCIE_PLLCFG4
This is connected to "CF_APLL_4" on SERDES ANA
Initial Settings required prior to power up sequence:
PCIE: 0000 609C -- SATA: 0000 0000 (both modes)
PCIE_PLLSTATUS
Initial Settings required prior to power up sequence:
PCIE_RXSTATUS
PCIE SerDes Receive Status register
PCIE_TXSTATUS
PCIE SerDes Transmit Status register
SATA_PLLCFG0
SATA PLL Configuration 0. Note: Please note that this
registers s reset behavior depends upon the Reset
Isolation Register (RESET_ISO) settings
SATA_PLLCFG1
SATA PLL Configuration 1. Note: Please note that this
registers s reset behavior depends upon the Reset
Isolation Register (RESET_ISO) settings.
SATA_PLLCFG2
SATA PLL Configuration 2. Note: Please note that this
registers s reset behavior depends upon the Reset
Isolation Register (RESET_ISO) settings.
SATA_PLLCFG3
SATA_PLLCFG3 Description. Note: Please note that this
registers s reset behavior depends upon the Reset
Isolation Register (RESET_ISO) settings.
SATA_PLLCFG4
5PCIe PLL Configuration 4. Note: Please note that this
registers s reset behavior depends upon the Reset
Isolation Register (RESET_ISO) settings.
SATA_PLLSTATUS
SATA PLL Status
SATA_RXSTATUS
SATA RX Status.
SATA_TXSTATUS
SATA TX Status. Note: Please note that this registers s
reset behavior depends upon the Reset Isolation
Register (RESET_ISO) settings.
SATA_TESTCFG
SATA TEST Config.
VDD_MPU_OPP_050
Ntarget value for OPP50.
VDD_MPU_OPP_100
Ntarget value for OPP100.
VDD_MPU_OPP_120
Ntarget value for OPP120.
VDD_MPU_OPP_166
Ntarget value for OPP166.
Section
Section 3.2.45
Section 3.2.46
Section 3.2.47
Section 3.2.48
Section 3.2.49
Section 3.2.50
Section 3.2.51
Section 3.2.52
Section 3.2.53
Section 3.2.54
Section 3.2.55
Section 3.2.56
Section 3.2.57
Section 21.5.1
Section 21.5.2
Section 21.5.3
Section 21.5.4
Section 21.5.5
Section 21.5.6
Section 21.5.7
Section 21.5.8
Section 21.5.9
Section 3.2.65
Section 3.2.66
Section 3.2.67
Section 3.2.68
SPRUGZ8D – 14 November 2011 – Revised April 2013
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