SPRUGZ8D Datasheet, PDF (2764/3016 Pages) Texas Instruments – Technical Reference Manual

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25.5.7 Subsystem Reset Considerations
The USB Subsystem controller can be reset by two sources: hardware reset and the soft reset.
25.5.7.1 Software Reset Considerations
When the soft reset bit in the USBSS SYSCONFIG register is set, all the USB controller registers and
DMA operations are reset. The bit is cleared automatically.
A software reset on the CPU does not affect the register values and operation of the USB controller.
25.5.7.2 Hardware Reset Considerations
When a hardware reset is asserted, all the registers are set to their default values.
25.5.8 Clock, PLL, and PHY Initialization
Prior to configuring the USB Module Registers, the device USB SubSystem and PHY are required to be
released from reset, provided with clocks as well as configured with appropriate settings. Not all registers
related for this task are captured within this document. Please refer to the Power, Reset and Clock
Manager (PRCM) for clocking and Control Module for PHY configuration registers definitions.
Note: The following initialization makes use of the software option where USB role is controlled by
firmware programming USBx Mode Register.
Clock Related Configuration:
*0x48180B10 &= 0xFFFFFF9F; // RM_DEFAULT_RSTCTRL (Release USB Module from Reset)
while ((0x48180B14 & 0x00000060)>>5)!=0x3); // Wait until Module comes out of Reset
*0x48180B14 |= 0x00000060; // RM_DEFAULT_RSTST (Clear Reset Presence)
*0x48181400 = 0x2; // CM_ALWON_L3_SLOW_CLKSTCTRL (Enable Interconnect Clock)
*0x48180558 = 0x2; // CM_DEFAULT_USB_CLKCTRL (Enable USB OCP Clock)
while(((*0x48180558) & 0x70000)>>16)==0x7); // Wait until USB Module is Ready
USB PLL Related:
PLL_SUBSYS_BASE = 0x481C5000;
USB_PLL_BASE = PLL_SUBSYS_BASE + 0x260;
/*Output clock frequency from PLL (according to above function call) = (((OSC
frequency/(N+1))*M)/M2) = (((20MHz/(19+1))*960)/1) = 960MHz*/
*(0x481C5270) = 0x00010013; // USBPLL_M2NDIV
*(0x481C5274) = 0x000003C0; // USBPLL_MN2DIV
/* Load M2, N2 dividers of ADPLL */
*(0x481C526C) = 0x00000001; // USBPLL_TENABLEDIV
// Toggle to Complete Load
*(0x481C526C) = 0x00000000; // USBPLL_TENABLEDIV
/* Load M, N dividers of ADPLL */
*(0x481C5268) = 0x00000001; // USBPLL_TENABLE
// Toggle to Complete Load
*(0x481C5268) = 0x00000000; // USBPLL_TENABLE
*(0x481C5264) = ((*(0x481C5264) & 0xff7fe3ff) | 0x200a080a); // USBPLL_CLKCTRL
/* Wait for phase and freq lock */
while (((*(0x481C5284)) & 0x00000600) != 0x00000600); // USBPLL_STATUS
USB PHY Related
// Clear bits 0,1,8,9,15,16,23
*(48140620) & = ~(0x00818303); // USB_CTRL0
// Set bits 6,7,10,13,14,17,18,19,20
*(48140620) |= 0x001E64C0; // USB_CTRL0
Firmware is now ready to continue programming the USB Controllers.
2764
Universal Serial Bus Subsystem (USBSS)
SPRUGZ8D – 14 November 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated
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