SPRUGZ8D Datasheet, PDF (1519/3016 Pages) Texas Instruments – Technical Reference Manual

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Registers
9.4.1.33 CPSW Port 2 TX Header Priority to Switch Priority Mapping Register (P2_TX_PRI_MAP) (0x0A0)
31
30
Reserved
R-0
Figure 9-53. CPSW Port 2 TX Header Priority to Switch Priority Mapping Register
(P2_TX_PRI_MAP)
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PRI7
Reserved
PRI6
Reserved
PRI5
Reserved
PRI4
R/W-3h
R-0
R/W-3h
R-0
R/W-2h
R-0
R/W-2h
15
14
13
12
11
10
9
8
Reserved
PRI3
Reserved
PRI2
R-0
R/W-1
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
7
6
Reserved
R-0
5
4
PRI1
R/W-0
3
2
Reserved
R-0
1
0
PRI0
R/W-1
Table 9-60. CPSW Port 2 TX Header Priority to Switch Priority Mapping Register (P2_TX_PRI_MAP)
Field Descriptions
Bit
31-30
29-28
27-26
25-24
23-22
21-20
19-18
17-16
15-14
13-12
11-10
9-8
7-6
5-4
3-2
1-0
Field
Reserved
PRI7
Reserved
PRI6
Reserved
PRI5
Reserved
PRI4
Reserved
PRI3
Reserved
PRI2
Reserved
PRI1
Reserved
PRI0
Value
0
0-3h
0
0-3h
0
0-3h
0
0-3h
0
0-3h
0
0-3h
0
0-3h
0
0-3h
Description
Read as zero.
Priority 7. A packet header priority of 7 is given this switch queue priority.
Read as zero.
Priority 6. A packet header priority of 6 is given this switch queue priority.
Read as zero.
Priority 5. A packet header priority of 5 is given this switch queue priority.
Read as zero.
Priority 4. A packet header priority of 4 is given this switch queue priority.
Read as zero.
Priority 3. A packet header priority of 3 is given this switch queue priority.
Read as zero.
Priority 2. A packet header priority of 2 is given this switch queue priority.
Read as zero.
Priority 1. A packet header priority of 1 is given this switch queue priority.
Read as zero.
Priority 0. A packet header priority of 0 is given this switch queue priority.
SPRUGZ8D – 14 November 2011 – Revised April 2013
3PSW Ethernet Subsystem (EMAC)
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