SPRUGZ8D Datasheet, PDF (3001/3016 Pages) Texas Instruments – Technical Reference Manual

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26.4.5 WDT_WIER Register
The WDT_WIERs register controls (enable/disable) the interrupt events.
It is shown and described in the figure and table below.
Watchdog Timer Registers
Figure 26-8. WDT_WIER Register
31
2
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
1
DLY_IT_ENA
R/W-0
0
OVF_IT_ENA
R/W-0
Bit Field
31-2 Reserved
1 DLY_IT_ENA
0 OVF_IT_ENA
Table 26-16. WDT_WIER Register Field Descriptions
Type
R
R/W
R/W
Reset
0
0
0
Description
Reads return 0.
Delay interrupt enable/disable
0 = Disable delay interrupt.
1 = Enable delay interrupt.
Overflow interrupt enable/disable
0 = Disable overflow interrupt.
1 = Enable overflow interrupt.
26.4.6 WDT_WCLR Register
The WDT_WCLR register controls the prescaler stage of the counter.
It is shown and descirbed in the figure and table below.
Figure 26-9. WDT_WCLR Register
31
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
654
2
PRE
PTV
R/W-1 R/W-0
0
Rsvd
R-0
Bit Field
31-6 Reserved
5 PRE
4-2 PTV
1-0 Reserved
Table 26-17. WDT_WCLR Register Field Descriptions
Type
R
R/W
R/W
R
Reset
0
1
0
0
Description
Reads return 0.
Prescaler enable/disable configuration
0 = Prescaler disabled
1 = Prescaler enabled
Prescaler value
The timer counter is prescaled with the
value: 2**PTV.
Example: PTV = 3 then counter increases
value if started after 8 functional clock
periods.
On reset, it is loaded from
PI_PTV_RESET_VALUE input port.
Write 0s for future compatibility. Reads
return 0.
SPRUGZ8D – 14 November 2011 – Revised April 2013
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Watchdog Timer 3001