TLK105 Datasheet, PDF (9/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
www.ti.com
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
3.2.2 Dual Supply Operation
When a 1.55V external power rail is available, the TLK10x can be configured as shown in Figure 3-2.
PFBOUT (pin 15) is left floating. The 1.55V external supply is connected to PFBIN1 (pin 13) and PFBIN2
(pin 24). Furthermore, to lower the power consumption, the internal regulator should be powered down by
writing ‘1’ to bit 15 of the VRCR register (0x00d0h).
3.3V
Supply
Pin 14
10mF 10nF 1nF 100pF ^(AVDD33)
1.55V
Supply
10mF
Floating
Pin 15
(PFBOUT)
Pin 13
10nF 1nF 100pF ^(PFBIN1)
1.55V
Supply
Pin 24
10mF 10nF 1nF 100pF ^(PFBIN2)
Pin 9
(RD–)
Pin 10
(RD+)
Pin 11
(TD–)
Pin 12
(TD+)
3.3V
Supply
49.9 W
49.9 W
3.3V
Supply
1mF
0.1mF
1mF
1:1
RD–
RD+
49.9 W
3.3V
Supply
1mF
49.9 W
0.1mF
TD–
TD+
1mF
0.1mF* ^{1:1 T1}
RJ45
3.3V
Supply
Pin 21
(VDD33_IO)
100pF 1nF 10nF 10mF
Figure 3-2. Power Connections for Dual Supply Operation
When operating with dual supplies, follow these guidelines:
• When powering up, ramp up the 3.3V supply before the 1.55V supply.
• When powering down, turn off the 1.55V supply before turning off the 3.3V supply.
• Use the external RESET pin after power up to reset the PHY.
• To use the internal power-on reset, PFBIN1 and PBIN2 must be operational less than 100ms after
3.3V rises to detect the internal RESET.
3.3 IO Pins Hi-Z State During Reset
The following IO or output pins are in hi-Z state when RESET is active (Low).
Pin Name
TXD_3
TX_EN
INT/PWDN
LED_LINK
MDIO
RX_DV
CRS
RX_ER
Type
IO
IO
IO
IO
IO
IO
IO
IO
Internal
PU/PD
PD
PD
PU
PU
PD
PU
PU
Pin Name
COL
RXD_0
RXD_1
RXD_2
RXD_3
TX_CLK
CLK25MHz_OUT
RX_CLK
Type
IO
IO
IO
IO
IO
O
O
O
Internal
PU/PD
PU
PD
PD
PD
PD
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Hardware Configuration
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