TLK105 Datasheet, PDF (77/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
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9.6 AC Specifications
9.6.1 Power Up Timing
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
Table 9-1. Power Up Timing
PARAMETER
Time from powerup to hardware-configuration pin
t₁
transition to output-driver function, using internal
POR (RESET pin tied high)
TEST CONDITIONS
MIN TYP MAX UNIT
100 270
ms
VDD
Hardware RESET
t1
Dual function pins
Become enabled
As outputs
Figure 9-1. Power Up Timing
NOTE
It is important to choose pullup and-or pulldown resistors for each of the hardware
configuration pins that provide fast RC time constants in order to latch in the proper value
prior to the pin transitioning to an output driver.
9.6.2 Reset Timing
PARAMETER
t₁
RESET pulse width
Table 9-2. Reset Timing
TEST CONDITIONS
XI Clock must be stable for minimum of 1ms
during RESET pulse low time.
MIN TYP MAX UNIT
1
µs
V_CC
XI Clock
t₁
Hardware
RESET
Figure 9-2. Reset Timing
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Electrical Specifications
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