TLK105 Datasheet, PDF (88/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
9.6.20 100Base-TX Signal Detect Timing
Table 9-20. 100Base-TX Signal Detect Timing
PARAMETER
t₁
SD Internal Turn-on Time
t₂
Internal Turn-off Time
TEST CONDITIONS
PMD Input Pair
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MIN TYP MAX UNIT
100 μs
200 μs
t₁
t₂
SD+ Intermal
NOTE: The signal amplitude on PMD Input Pair must be TP-PMD compliant.
Figure 9-20. 100Base-TX Signal Detect Timing
T0360-01
9.6.21 100Mbs Loopback Timing
Table 9-21. 100Mbs Loopback Timing
PARAMETER
t₁
TX_EN to RX_DV Loopback
TEST CONDITIONS
100Mbs external loopback
100Mbs external loopback – fast RX_DV mode
100Mbs analog loopback
100Mbs PCS Input loop back
100Mbs MII loop back
MIN TYP MAX UNIT
241 242 243
201 202 203
232 233 234 ns
120 121 122
8
9
10
88
Electrical Specifications
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