TLK105 Datasheet, PDF (82/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
9.6.9 100Base-TX Receive Packet Latency Timing
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Table 9-9. 100Base-TX Receive Packet Latency Timing
PARAMETER
t₁
Carrier Sense ON Delay⁽³⁾
t₂
Receive Data Latency
t₂
Receive data latency⁽⁴⁾
TEST CONDITIONS⁽¹⁾
100Mbs Normal mode
100Mbs Normal mode
100Mb normal mode with fast RXDV
detection ON
MIN TYP MAX UNIT⁽²⁾
14
bits
19
bits
15
bits
(1) PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
(2) 1 bit time = 10 ns in 100Mbs mode
(3) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
(4) Fast RXDV detection could be enabled by setting bit[1] of CR1 (address 0x0009).
PMD Input Pair IDLE
(J/K)
Data
CRS
RXD[3:0]
RX_DV
RX_ER
t₁
t₂
Figure 9-9. 100Base-TX Receive Packet Latency Timing
T0346-01
9.6.10 100Base-TX Receive Packet Deassertion Timing
Table 9-10. 100Base-TX Receive Packet Deassertion Timing
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
t₁
Carrier Sense OFF Delay⁽¹⁾
100Mbs Normal mode
19
bits ⁽²⁾
(1) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
(2) 1 bit time = 10 ns in 100Mbs mode
PMD Input Pair DATA
(T/R)
IDLE
t₁
CRS
Figure 9-10. 100Base-TX Receive Packet Deassertion Timing
T0347-01
82
Electrical Specifications
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