TLK105 Datasheet, PDF (28/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
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5.2.5 Descrambler
The descrambler is used to descramble the received NRZ data. The data is further deserialized and the
parallelized data is aligned to 5-bit code-groups and mapped into 4-bit nibbles. At initialization, the 100B-
TX descrambler uses the IDLE-symbols sequence to lock on the far-end scrambler state. During that time,
neither data transmission nor reception is enabled. After the far-end scrambler state is recovered, the
descrambler constantly monitors the data and checks whether it still synchronized. If, for any reason,
synchronization is lost, the descrambler tries to re-acquire synchronization using the IDLE symbols.
5.2.6 5B/4B Decoder and Nibble Alignment
The code-group decoder functions as a look up table that translates incoming 5-bit code-groups into 4-bit
nibbles. The code-group decoder first detects the Start of Stream Delimiter (SSD) /J/K/ code-group pair
preceded by IDLE code-groups at the start of a packet. Once the code group alignment is determined, it is
stored and used until the next start-of-frame. The decoder replaces the /J/K/ with the MAC preamble.
Specifically, the /J/K/ 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5-
bit code-groups are converted to the corresponding 4-bit nibbles for the duration of the entire packet. This
conversion ceases upon the detection of the /T/R/ code-group pair denoting the End-of-Stream Delimiter
(ESD) or with the reception of a minimum of two IDLE code-groups.
5.2.7 Timing Loop and Clock Recovery
The receiver must lock on the far-end transmitter clock in order to sample the data at the optimum timing.
The timing loop recovers the far-end clock frequency and offset from the received data samples and
tracks instantaneous phase drifts caused by timing jitter.
The TLK10x has a robust adaptive-timing loop (Tloop) mechanism that is responsible for tracking the Far-
End TX clock and adjusting the AFE sampling point to the incoming signal. The Tloop implements an
advanced tracking mechanism that when combined with different available phases, always keeps track of
the optimized sampling point for the data, and thus offers a robust RX path,tolerant to both PPM and
Jitter. The TLK10x is capable of dealing with PPM and jitter at levels far higher than those defined by the
standard.
5.2.8 Phase-Locked Loops (PLL)
In 10B-T the digital phase lock loop (DPLL) function recovers the far-end link-partner clock from the
received Manchester signal. The DPLL is able to combat clock jitter of up to ±18ns and frequency drifts of
±500ppm between the local PHY clock and the far-end clock. The DPLL feeds the decoder with a
decoded serial bit stream.
The integrated analog Phase-Locked Loop (PLL) provides the clocks to the analog and digital sections of
the PHY. The PLL is driven by an external reference clock (sourced at the XI,XO pins with a crystal
oscillator, or at XI with an external reference clock).
5.2.9 Link Monitor
The TLK10x implements the link monitor State Machine (SM) as defined by the IEEE 802.3 100Base-TX
Standard. In addition, the TLK10x enables several add-ons to the link monitor SM activated by
configuration bits. The new add-ons include the recovery state which enables the PHY to attempt recovery
in the event of a temporary energy-loss situation before entering the LINK_FAIL state, thus restarting the
whole link establishment procedure. This sequence allows significant reduction of the recovery time in
scenarios where the link loss is temporal.
In addition, the link monitor SM enables moving to the LINK_DOWN state based on descrambler
synchronization failure and not only on Signal_Status indication, which shortens the drop-link down time.
These add-ons are supplementary to the IEEE standard and are bypassed by default.
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Architecture
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