TLK105 Datasheet, PDF (79/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
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9.6.5 100Mb/s MII Receive Timing
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
Table 9-5. 100Mb/s MII Receive Timing
PARAMETER ⁽¹⁾
TEST CONDITIONS
MIN TYP MAX UNIT
t₁
RX_CLK High Time
t₂
RX_CLK Low Time
100Mbs Normal mode
t₃
RX_CLK to RXD[3:0], RX_DV, RX_ER Delay
100Mbs Normal mode
16
20
10
24 ns
30 ns
(1) RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high
and low times will not be violated.
t₁
t₂
RX_CLK
RXD[3:0]
RX_DV
RX_ER
t₃
Valid Data
Figure 9-5. 100Mb/s MII Receive Timing
T0342-01
9.6.6 100Base-TX Transmit Packet Latency Timing
Table 9-6. 100Base-TX Transmit Packet Latency Timing
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
t₁
TX_CLK to PMD Output Pair Latency
100Mbs Normal mode⁽¹⁾
4.8
bits ⁽²⁾
(1) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of
TX_EN to the first bit of the 'J' code group as output from the PMD Output Pair. 1 bit time = 10ns in 100Mbs mode.
(2) 1 bit time is equal 10 nS in 100 Mb/s mode.
TX_CLK
TX_EN
TXD
t₁
PMD Output Pair
IDLE
(J/K)
DATA
Figure 9-6. 100Base-TX Transmit Packet Latency Timing
T0343-01
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