TLK105 Datasheet, PDF (53/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
www.ti.com
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
BIT BIT NAME
3:2 Fast AN Sel
1 Fast RXDV
Detection
0 RESERVED
Table 8-13. Control register 1 (CR1), address 0x0009 (continued)
DEFAULT
0, RW
0, RW
DESCRIPTION
Fast Auto-Negotiation Select bits:
Fast AN
Select
Break
Link
Timer
Link Fail
Inhibit
Timer
Auto-Neg Wait Timer
<00>
80
50
35
<01>
120
75
50
<10>
240
150
100
<11>
NA
NA
NA
Adjusting these bits reduces the time it takes to Auto-negotiate between two PHYs. In
Fast AN mode, both PHYs should be configured to the same configuration. These 2 bits
define the duration for each state of the Auto Negotiation process according to the table
above. The new duration time must be enabled by setting “Fast AN En” - bit 4 of this
register. Note: Using this mode in cases where both link partners are not configured to
the same Fast Auto-negotiation configuration might produce scenarios with unexpected
behavior.
Fast RXDV Detection:
1 = Enable assertion high of RX_DV on receive packet due to detection of /J/ symbol
only. If a consecutive /K/ does not appear, RX_ER is generated.
0 = Disable Fast RX_DV detection. The PHY operates in normal mode - RX_DV
assertion after detection of /J/K/.
1, RW
RESERVED
Copyright © 2012–2013, Texas Instruments Incorporated
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