TLK105 Datasheet, PDF (67/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
www.ti.com
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
8.16 Cable Diagnostic Control Register (CDCR)
Table 8-31. Cable Diagnostic Control Register (CDCR), address 0x001E
BIT NAME
DEFAULT
15 Diagnostic Start 0,RW
14:10 RESERVED
9:8 Link Quality
<000
00>,RO
<<00>,RO
7:4 RESERVED
0,RO
3:2 RESERVED
00>,RO
1 Diagnostic Done 0,RO
0 Diagnostic Fail 0,RO
FUNCTION
Cable Diagnostic Process Start:
1 = Start execute cable measurement
0 = Cable Diagnostic is disabled
Diagnostic Start bit is cleared with raise of Diagnostic Done indication.
RESERVED: Writes ignored, read as 0.
Link Quality Indication
<00> = Reserved
<01> = Good Quality Link Indication
<10> = Mid Quality Link Indication
<11> = Poor Quality Link Indication
The value of these bits are valid only when link is active – While reading “1” from “Link Status” bit
0 on PHYSTS register (0x0010).
RESERVED: Writes ignored, read as 0.
RESERVED: Writes ignored, read as 0.
Cable Diagnostic Process Done:
1 = Indication that cable measurement process completed
0 = Diagnostic has not completed
Cable Diagnostic Process Fail:
1 = Indication that cable measurement process failed
0 = Diagnostic has not failed
8.17 PHY Reset Control Register (PHYRCR)
This register provides ability to the system to reset or restart the PHY by register access.
Table 8-32. PHY Reset Control Register (PHYRCR), address 0x001F
BIT NAME
15 Software Reset
14 Software
Restart
13:0 RESERVED
DEFAULT
0, RW,SC
0, RW,SC
<00 0000 0000
0000>, RO
FUNCTION
Software Reset:
1 = Reset PHY. Allow the system to reset the PHY using register access. This bit is self cleared
and has same effect as Hardware reset pin.
0 = Normal Operation
Software Restart:
1 = Reset PHY. Allow the system to restart the PHY using register access. This bit is self
cleared and resets all PHY circuitry except the registers.
0 = Normal Operation
Writes ignored, read as 0
8.18 TX_CLK Phase Shift Register (TXCPSR)
This register allows programming the phase of the MII transmit clock (TX_CLK pin). The TX_CLK has a
fixed phase to the XI pin. However the default phase, while fixed, may not be ideal for all systems,
therefore this register may be used by the system to align the reference clock (XI pin) to the TX_CLK. The
phase shift value is in 4ns units. The phase shift value should be between 0 and 10 (0ns to 40ns). If value
greater than 10 is written, the update value will be the written value modulo 10.
Table 8-33. TX_CLK Phase Shift Register (TXCPSR), address 0x0042
BIT NAME
DEFAULT
15:5 RESERVED <0000 0000
000>, RO
4 Phase Shift 0,RW,SC
Enable
FUNCTION
RESERVED: Writes ignored, read as 0
TX Clock Phase Shift Enable:
1 = Perform Phase Shift to the TX_CLK according to the value written to Phase Shift Value in bits
[4:0].
0 = No change in TX Clock phase
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