TLK105 Datasheet, PDF (66/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
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Table 8-29. BIST Control and Status Register 1 (BICSR1), address 0x001B (continued)
BIT BIT NAME
7:0 BIST IPG
Length
DEFAULT
<0111 1101>,
RW
DESCRIPTION
BIST IPG Length:
Inter Packet Gap (IPG) Length defines the size of the gap (in bytes) between any 2 successive
packets generated by the BIST. Default value is 0x7D which is equal to 125 bytes
8.15 BIST Control and Status Register2 (BICSR2)
This register allows programming the length of the generated packets in bytes for the BIST mechanism.
Table 8-30. BIST Control and Status Register 2 (BICSR2), address 0x001C
BIT
BIT NAME
15:11 RESERVED
10:0 BIST Packet
Length
DEFAULT
<0000 0>,
RO
0X5DC,RW
DESCRIPTION
RESERVED: Writes ignored, read as 0.
BIST Packet Length:
Length of the generated BIST packets. The value of this register defines the size (in bytes) of
every packet that generated by the BIST. Default value is 0x5DC which is equal to 1500 bytes
66
Register Block
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