TLK105 Datasheet, PDF (58/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
www.ti.com
Table 8-18. PHY Status Register (PHYSTS), address 0x0010 (continued)
BIT NAME
DEFAULT
DESCRIPTION
4 Auto-Neg
Status
0,RO
Auto-Negotiation Status:
1 = Auto-Negotiation complete
0 = Auto-Negotiation not complete
3 MII Loopback 0,RO
Status
MII Loopback:
1 = Loopback active (enabled)
0 = Normal operation
2 Duplex Status 0,RO
Duplex Status:
1 = Full duplex mode
0 = Half duplex mode
This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes. Therefore, it
is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation
is disabled and there is a valid link.
1 Speed Status 0,RO
Speed Status:
1 = 10 Mb/s mode
0 = 100 Mb/s mode
This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced Modes.
Speed Status is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if
Auto-Negotiation is disabled and there is a valid link.
0 Link Status 0,RO
Link Status:
1 = Valid link established (for either 10 or 100 Mb/s operation). This bit is a duplicate of the Link
Status bit in the BMSR register (0x0001).
0 = Link not established
This bit will not be cleared upon a read of the PHYSTS register.
8.4 PHY Specific Control Register (PHYSCR)
This register implements the PHY Specific Control register. This register allows access to general
functionality inside the PHY to enable operation in reduced power modes and control interrupt mechanism.
Table 8-19. PHY Specific Control Register (PHYSCR), address 0x0011
BIT NAME
15 Disable PLL
14 PS Enable
13:12 PS Modes
DEFAULT DESCRIPTION
0,RW
Disable PLL:
1 = Disable internal clocks Circuitries
0 = Normal mode of operation
Note: Clock Circuitry can be disabled only in IEEE power-down mode
0,RW
Power Save Modes Enable:
1 = Enable power save modes
0 = Normal mode of operation
<00>,RW Power Save Modes:
Power Mode
<00>
<01>
<10>
<11>
Name
Normal
IEEE power
down
Active Sleep
Passive
Sleep
Description
Normal operation mode. PHY is fully functional
Low Power mode that shut down all internal circuitry
beside SMI functionality.
Low Power Active WOL mode that shut down all internal
circuitry beside SMI and energy detect functionalities. In
this mode the PHY sends NLP every 1.4 Sec to wake up
link-partner. Automatic power-up is done when link partner
is detected.
Low Power WOL mode that shut down all internal circuitry
beside SMI and energy detect functionalities. Automatic
power-up is done when link partner is detected.
58
Register Block
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