TLK105 Datasheet, PDF (3/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
www.ti.com
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
1 Introduction .............................................. 1
1.1 Features ............................................. 1
1.2 Applications .......................................... 1
1.3 Device Overview ..................................... 1
2 Pin Descriptions ......................................... 4
2.1 Pin Layout ........................................... 4
2.2 Serial Management Interface (SMI) ................. 5
2.3 MAC Data Interface .................................. 5
2.4 10Mbs and 100Mbs PMD Interface .................. 6
2.5 Clock Interface ....................................... 6
2.6 LED Interface ........................................ 6
2.7 Reset and Power Down ............................. 6
2.8 Power and Bias Connections ........................ 7
3 Hardware Configuration ............................... 7
3.1 Bootstrap Configuration .............................. 7
3.2 Power Supply Configuration ......................... 8
3.3 IO Pins Hi-Z State During Reset ..................... 9
3.4 Auto-Negotiation .................................... 10
3.5 Auto-MDIX .......................................... 10
3.6 MII Isolate Mode .................................... 11
3.7 PHY Address ....................................... 11
3.8 LED Interface ....................................... 12
3.9 Loopback Functionality ............................. 13
3.10 BIST ................................................ 15
3.11 Cable Diagnostics .................................. 15
4 Interfaces ................................................ 17
4.1 Media Independent Interface (MII) ................. 17
4.2 Reduced Media Independent Interface (RMII) ..... 18
4.3 Serial Management Interface ....................... 20
5 Architecture ............................................. 24
5.1 100Base-TX Transmit Path ......................... 24
5.2 100Base-TX Receive Path ......................... 27
5.3 10Base-T Receive Path ............................ 29
5.4 Auto Negotiation .................................... 30
5.5 Link Down Functionality ............................ 31
6 Reset and Power Down Operation ................. 33
6.1 Hardware Reset .................................... 33
6.2 Software Reset ..................................... 33
6.3 Power Down/Interrupt .............................. 33
6.4 Power Save Modes ................................. 34
7 Design Guidelines ..................................... 35
7.1 TPI Network Circuit ................................. 35
7.2 Clock In (XI) Requirements ......................... 35
7.3 Thermal Vias Recommendation .................... 37
8 Register Block ......................................... 38
8.1 Register Definition .................................. 43
8.2 Extended Register Addressing ..................... 55
8.3 PHY Status Register (PHYSTS) ................... 57
8.4 PHY Specific Control Register (PHYSCR) ......... 58
8.5 MII Interrupt Status Register 1 (MISR1) ............ 59
8.6 MII Interrupt Status Register 2 (MISR2) ............ 60
8.7 False Carrier Sense Counter Register (FCSCR) ... 61
8.8 Receiver Error Counter Register (RECR) .......... 61
8.9 BIST Control Register (BISCR) .................... 61
8.10 RMII Control and Status Register (RCSR) ......... 62
8.11 LED Control Register (LEDCR) .................... 64
8.12 PHY Control Register (PHYCR) .................... 64
8.13 10Base-T Status/Control Register (10BTSCR) .... 65
8.14 BIST Control and Status Register 1 (BICSR1) ..... 65
8.15 BIST Control and Status Register2 (BICSR2) ..... 66
8.16 Cable Diagnostic Control Register (CDCR) ........ 67
8.17 PHY Reset Control Register (PHYRCR) ........... 67
8.18 TX_CLK Phase Shift Register (TXCPSR) .......... 67
8.19 Voltage Regulator Control Register (VRCR) ....... 68
8.20 Cable Diagnostic Configuration/Result Registers
(TLK106) ............................................ 68
9 Electrical Specifications ............................. 74
9.1 ABSOLUTE MAXIMUM RATINGS ................. 74
9.2 RECOMMENDED OPERATING CONDITIONS .... 74
9.3 THERMAL CHARACTERISTICS ................... 74
9.4 DC CHARACTERISTICS
9.5 POWER SUPPLY CHARACTERISTICS
9.6 AC Specifications
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