TLK105 Datasheet, PDF (35/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
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7 Design Guidelines
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
7.1 TPI Network Circuit
Figure 7-1 shows the recommended circuit for a 10/100Mbs twisted pair interface. Below is a partial
list of recommended transformers. Variations with PCB and component characteristics require that
the application be tested to verify that the circuit meets the requirements of the intended application.
• Pulse H1102
• Pulse HX1188
RD–
49.9 W
RD+
49.9 W
Vdd
0.1 mF
Vdd
Common-mode chokes
may be required.
1:1
RD–
RD+
1mF
TD–
Vdd
49.9 W
49.9 W
TD+
0.1 mF
Place resistors and capacitors close to the device.
TD–
TD+
1mF
0.1mF* ^{1:1 T1}
RJ45
Note: Center tap is connected to Vdd
* Place capacitors close to the
transformer center taps
All values are typical and are ±1%
Figure 7-1. 10/100Mbs Twisted Pair Interface
7.2 Clock In (XI) Requirements
The TLK10x supports an external CMOS-level oscillator source or an internal oscillator with an external
crystal.
7.2.1 Oscillator
If an external clock source is used, XI should be tied to the clock source and XO should be left floating.
The amplitude of the oscillator should be a nominal voltage of 3.3V.
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