TLK105 Datasheet, PDF (33/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
www.ti.com
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
6 Reset and Power Down Operation
The TLK10x includes an internal power-on-reset (POR) function, and therefore does not need an explicit
reset for normal operation after power up.
At power-up, if required by the system, the RESET pin (active low) should be de-asserted 200µs after the
power is ramped up to allow the internal circuits to settle and for the internal regulators to stabilize. If
required during normal operation, the device can be reset by a hardware or software reset.
6.1 Hardware Reset
A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1μs, to
RESET. This pulse resets the device such that all registers are reinitialized to default values, and the
hardware configuration values are re-latched into the device (similar to the power-up/reset operation). The
time from the point when the reset pin is de-asserted to the point when the reset has concluded internally
is approximately 200µs.
6.2 Software Reset
An IEEE registers software reset is accomplished by setting the reset bit (bit 15) of the BMCR register
(0x0000h). This bit only resets the IEEE-defined standard registers in the address space 0x00h to 0x07h.
A global software reset is accomplished by setting bit 15 of register PHYRCR (0x001F) to ‘1’. This bit
resets all the internal circuits in the PHY including IEEE-defined registers (0x00h to 0x07h) and all the
extended registers. The global software reset resets the device such that all registers are reset to default
values and the hardware configuration values are maintained.
A global software restart is accomplished by setting bit 14 of register PHYRCR (0x001F) to ‘1’. This
action resets all the PHY circuits except the registers in the Register File.
The time from the point when the resets/restart bits are set to the point when the software resets/restart
has concluded is approximately 200µs. TI recommends that the software driver code must wait 500µs
following software reset before allowing further serial MII operations with the TLK10x.
6.3 Power Down/Interrupt
The Power Down and Interrupt functions are multiplexed on pin 8 of the device. By default, this pin
functions as a power down input and the interrupt function is disabled. This pin can be configured as an
interrupt output pin by setting bit 0 (INT_OE) to ‘1’ in the PHYSCR (0x0011h) register. The PHYSCR
register is also used to enable and set the polarity of the interrupt.
6.3.1 Power Down Control Mode
The INT/PWDN pin can be asserted low to put the device in a Power Down mode. An external control
signal can be used to drive the pin low, overcoming the weak internal pull-up resistor. Alternatively, the
device can be configured to initialize into a Power Down state by use of an external pulldown resistor on
the INT/PWDN pin.
6.3.2 Interrupt Mechanisms
The interrupt function is controlled via register access. All interrupt sources are disabled by default. The
MISR1 (0x0012) and MISR2 (0x0013) registers provide independent interrupt enable bits for the various
interrupts supported by the TLK10x. The INT/PWDN pin is asynchronously asserted low when an interrupt
condition occurs. The source of the interrupt can be determined by reading the interrupt status registers
MISR1 (0x0012h) and MISR2 (0x0013). One or more bits in the MISR registers will be set, indicating all
currently-pending interrupts. Reading the MISR registers clears ALL pending interrupts.
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