TLK105 Datasheet, PDF (60/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
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Table 8-20. MII Interrupt Status Register 1 (MISR1), address 0x0012 (continued)
BIT
NAME
11 Duplex Mode Changed INT
10 Auto-Negotiation Completed INT
9 FC HF INT
8 RE HF INT
7:6 RESERVED
5 Link Status Changed EN
4 Speed Changed EN
3 Duplex Mode Changed EN
2 Auto-Negotiation Completed EN
1 FC HF EN
0 RE HF EN
DEFAULT
0,RO, COR
0,RO, COR
0,RO, COR
0,RO, COR
<00>, RO
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
DESCRIPTION
Change of duplex status interrupt:
1 = Duplex status change interrupt is pending
0 = No change of duplex status
Auto-Negotiation Complete interrupt:
1 = Auto-negotiation complete interrupt is pending.
0 = No Auto-negotiation complete event is pending
False Carrier Counter half-full interrupt:
1 = False carrier counter (Register FCSCR, address 0x0014) exceeds half-
full interrupt is pending
0 = False carrier counter half-full event is not pending
Receive Error Counter half-full interrupt:
1 = Receive error counter (Register RECR, address 0x0015) exceeds half
full interrupt is pending
0 = No Receive error counter half full event pending
RESERVED: Writes ignored, read as 0.
Enable Interrupt on change of link status
Enable Interrupt on change of speed status
Enable Interrupt on change of duplex status
Enable Interrupt on Auto-negotiation complete event
Enable Interrupt on False Carrier Counter Register half-full event
Enable Interrupt on Receive Error Counter Register half-full event
8.6 MII Interrupt Status Register 2 (MISR2)
This register contains events status and enables for the interrupt function. If an event has occurred since
the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the
register is set, an interrupt will be generated if the event occurs. The PHYSCR register (0x0011) bits 1 and
0 must also be set to allow interrupts. The status indications in this register will be set even if the interrupt
is not enabled.
Table 8-21. MII Interrupt Status Register 2 (MISR2), address 0x0013
BIT
NAME
15 RESERVED
14 AN Error INT
13 Page Rec INT
12 Loopback FIFO OF/UF INT
11 MDI Crossover Changed INT
10 Sleep Mode INT
9 Polarity Changed INT
8 Jabber Detect INT
7 RESERVED
6 AN Error EN
DEFAULT
0, RO
0,RO, COR
0,RO, COR
0,RO, COR
0,RO, COR
0,RO, COR
0,RO, COR
0,RO
0,RW
0,RW
DESCRIPTION
RESERVED: Writes ignored, read as 0.
Auto-Negotiation Error Interrupt:
1 = Auto-negotiation error interrupt is pending
0 = No Auto-negotiation error event pending
Page Receive Interrupt:
1 = Page has been received
0 = Page has not been received
Loopback FIFO Overflow/Underflow Event Interrupt:
1 = FIFO Overflow/Underflow event interrupt pending
0 = No FIFO Overflow/Underflow event pending
MDI/MDIX Crossover Status Changed Interrupt:
1 = MDI crossover status changed interrupt is pending
0 = MDI crossover status has not changed
Sleep Mode Event Interrupt:
1 = Sleep Mode event interrupt is pending
0 = No sleep mode event pending
Polarity Changed Interrupt:
1 = Data polarity changed interrupt pending
0 = No Data polarity event pending
Jabber Detect Event Interrupt:
1 = Jabber detect event interrupt pending
0 = No Jabber detect event pending
RESERVED: Writes ignored, read as 0
Enable Interrupt on Auto-Negotiation error event
60
Register Block
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