TLK105 Datasheet, PDF (6/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
www.ti.com
2.4 10Mbs and 100Mbs PMD Interface
PIN
NAME
NO.
TD–, TD+ 11, 12
RD–, RD+ 9, 10
TYPE
I/O
I/O
DESCRIPTION
Differential common driver transmit output (PMD Output Pair): These differential outputs are
automatically configured to either 10Base-T or 100Base-TX signaling.
In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 3.3V
bias for operation.
Differential receive input (PMD Input Pair): These differential inputs are automatically configured to
accept either 100Base-TX or 10Base-T signaling.
In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair. These pins require
3.3V bias for operation.
2.5 Clock Interface
PIN
NAME
NO.
XI
23
XO
22
TYPE
DESCRIPTION
CRYSTAL/OSCILLATOR INPUT:
MII reference clock: Reference clock. 25MHz ±50ppm-tolerance crystal reference or oscillator input. The
I
device supports either an external crystal resonator connected across pins XI and XO, or an external
CMOS-level oscillator source connected to pin XI only.
RMII reference clock: Primary clock reference input for the RMII mode. The input must be connected to a
50MHz ±50ppm-tolerance CMOS-level oscillator source.
O
CRYSTAL OUTPUT: Reference Clock output. XO pin is used for crystal only. This pin should be left floating
when an oscillator input is connected to XI.
2.6 LED Interface
(See Table 3-3 for LED Mode Selection)
PIN
NAME
LED_LINK /
AN_0
TYPE
NO.
DESCRIPTION
LED Pin to indicate status
Mode 1
17 S, O, PU
Mode 2
LINK Indication LED: Indicates the status of the link. When the link is good, the LED
is ON.
ACT indication LED: Indicates transmit and receive activity in addition to the status
of the Link. The LED is ON when Link is good. The LED blinks when the transmitter
or receiver is active.
2.7 Reset and Power Down
PIN
NAME
RESET
INT / PWDN
TYPE
NO.
DESCRIPTION
This pin is an active-low reset input that initializes or re-initializes all the internal registers of the
18
I, PU TLK10x. Asserting this pin low for at least 1 µs will force a reset process to occur. All jumper
options are reinitialized as well.
Register access is required for this pin to be configured either as power down or as an interrupt.
The default function of this pin is power down.
When this pin is configured for a power down function, an active low signal on this pin places the
8 IO, OD, PU device in power down mode.
When this pin is configured as an interrupt pin, then this pin is asserted low when an interrupt
condition occurs. The pin has an open-drain output with a weak internal pull-up. Some
applications may require an external pull-up resistor.
6
Pin Descriptions
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLK105 TLK106