TLK105 Datasheet, PDF (4/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
www.ti.com
2 Pin Descriptions
The TLK10x pins fall into the following interface categories (subsequent sections describe each interface):
• Serial Management Interface
• MAC Data Interface
• Clock Interface
• LED Interface
• Reset and Power Down
• Bootstrap Configuration Inputs
• 10/100Mbs PMD Interface
• Special Connect Pins
• Power and Ground pins
Note: Configuration pin option. See Section 3.1 for Jumper Definitions.
The definitions below define the functionality of each pin.
Type: I
Type: O
Type: I/O
Type: OD
Type: PD, PU
Type: S
Input
Output
Input/Output
Open Drain
Internal Pulldown/Pullup
Configuration Pin (All configuration pins have weak internal pullups or pulldowns.
Use an external 2.2kΩ resistor if you need a different default value. See
Section 3.1 for details.)
2.1 Pin Layout
RXD_3 / PHYAD4
TX_CLK
TX_EN
TXD_0
TXD_1
TXD_2
TXD_3
INT / PWDN
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
21
GND
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
PFBIN2
XI
XO
VDD33_IO
MDC
MDIO
RESET
LED_LINK / AN_0
4
Pin Descriptions
Figure 2-1. TLK10x PIN DIAGRAM, TOP VIEW
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