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TLK105 Datasheet, PDF (80/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver
TLK105
TLK106
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
9.6.7 100Base-TX Transmit Packet Deassertion Timing
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Table 9-7. 100Base-TX Transmit Packet Deassertion Timing
PARAMETER
TEST CONDITIONS
t1
TX_CLK to PMD Output Pair deassertion
100Mbs Normal mode
MIN TYP
4.6
MAX UNIT
bits
TX_CLK
TX_EN
TXD
t1
PMD Output Pair
DATA
DATA
(T/R)
(T/R)
IDLE
IDLE
T0344-01
Figure 9-7. 100Base-TX Transmit Packet Deassertion Timing
80
Electrical Specifications
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