TLK105 Datasheet, PDF (7/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
www.ti.com
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
2.8 Power and Bias Connections
PIN
NAME
RBIAS
PFBOUT
PFBIN1
PFBIN2
VDD33_IO
AVDD33
GND
NO.
16
15
13
24
21
14
Ground
Pad
TYPE
I
O
I
P
P
P
DESCRIPTION
Bias Resistor Connection: Use a 4.87kΩ 1% resistor connected from RBIAS to GND.
Power Feedback Output: Place 10µf and 0.1μF capacitors (ceramic preferred) close to PFBOUT.
In single-supply operation, connect this pin to PFBIN1 and PFBIN2 (pin 13 and pin 24). See Figure 3-1
for proper placement.
In multiple supply operation, this pin is not used.
Power Feedback Input: These pins are fed with power from PFBOUT (pin 15) in single supply
operation.
In multiple supply operation, connect a 1.55V external power supply to these pins. Connect a small
capacitor of 0.1µF close to each pin. To power down the internal linear regulator, write to register
0x00d0.
I/O 3.3V Supply
Analog 3.3V power supply
Ground Pad
3 Hardware Configuration
This section includes information on the various configuration options available with the TLK10x. The
configuration options described below include:
• Bootstrap Configuration
• Power Supply Configuration
• IO Pins Hi-Z State During Reset
• Auto-Negotiation
• Auto-MDIX
• MII Isolate mode
• PHY Address
• LED Interface
• Loopback Functionality
• BIST
• Cable Diagnostics (TLK106 only)
3.1 Bootstrap Configuration
Bootstrap configuration is a convenient way to configure the TLK10x into specific modes of operation.
Some of the functional pins are used as configuration inputs. The logic states of these pins are sampled
during reset and are used to configure the device into specific modes of operation. The table below
describes bootstrap configuration.
A 2.2kΩ resistor is used for pull-down or pull-up to change the default configuration. If the default option is
desired, then there is no need for external pull-up or pull down resistors. Because these pins may have
alternate functions after reset is deasserted, they must not be connected directly to VCC or GND.
PIN
NAME
PHYAD0 (COL)
PHYAD1 (RXD_0)
PHYAD2 (RXD_1)
PHYAD3 (RXD_2)
PHYAD4 (RXD_3)
AN_0 (LED_LINK)
LED_CFG (CRS)
TYPE
NO.
DESCRIPTION
29
PHY Address [4:0]: The TLK10x provides five PHY address pins, the states of which are
30
31
32
S, O, PD /
PU
latched into an internal register at system hardware reset. The TLK10x supports PHY
Address values 0 (<00000>) through 31 (<11111>). PHYAD[4:1] pins have weak internal
pull-down resistors, and PHYAD[0] has weak internal pull-up resistor, setting the default
1
PHYAD if no external resistors are connected.
17 S, O, PU ^{AN_0: FD-HD config. FD = pull up.}
The default wake-up is auto negotiation enable 100BT.
This option selects the operation mode of the LED LINK pin. Default is Mode 1. All modes
27 S, O, PU are also configurable via register access. See PHY Control Register (PHYCR), Address
0x0019.
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Hardware Configuration
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