TLK105 Datasheet, PDF (55/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
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SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
8.1.12 Control Register 3 (CR3)
BIT BIT NAME
15:7 RESERVED
6 Polarity
Swap
5 MDI/MDIX
Swap
4 RESERVED
3:0 Fast Link
Down Mode
Table 8-15. Control register 3 (CR3), address 0x000B
DEFAULT
0, RO
0, RW
0, RW
0, RW
0, RW
DESCRIPTION
RESERVED: Writes ignored, read as 0.
Polarity Swap:
1 = Inverted polarity on both pairs: TPTD+ ↔ TPTD-, TPRD+ ↔ TPRD-
0 = Normal polarity
Port Mirror function: To Enable port mirroring, set bit 5 and this bit high.
MDI/MDIX Swap:
1 = Swap MDI pairs (Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal (Receive on TPRD pair, Transmit on TPTD pair)
Port Mirror function: To Enable port mirroring, set this bit and bit 6 high.
RESERVED
Fast Link Down Modes:
Bit 3 Drop the link based on RX Error count of the MII interface – When a predefined number
of 32 RX Error occurrences in a 10µs interval is reached, the link will be dropped.
Bit 2 Drop the link based on MLT3 Errors count (Violation of the MLT3 coding in the DSP
output) – When a predefined number of 20 MLT3 Error occurrences in a 10µs interval is
reached, the link will be dropped.
Bit 1 Drop the link based on Low SNR Threshold – When a predefined number of 20
Threshold crossing occurrences in a 10µs interval is reached, the link will be dropped.
Bit 0 Drop the link based on Signal/Energy loss indication – When the Energy detector
indicates Energy Loss, the link will be dropped. Typical reaction time is 10µs.
The Fast Link Down function is an OR of all these 4 options, so the designer can enable
combinations of these conditions.
8.2 Extended Register Addressing
REGCR (0x000D) and ADDAR (0x000E) allow read/write access to the extended register set (addresses
above 0x000F) using indirect addressing.
• REGCR [15:14] = 00: A write to ADDAR modifies the extended register set address register. This
address register must be initialized in order to access any of the registers within the extended register
set.
• REGCR [15:14] = 01: A read/write to ADDAR operates on the register within the extended register set
selected (pointed to) by the value in the address register. The address register contents (pointer)
remain unchanged.
• REGCR [15:14] = 10: A read/write to ADDAR operates on the register within the extended register set
selected (pointed to) by the value in the address register. After that access is complete, for both reads
and writes, the value in the address register is incremented.
• REGCR [15:14] = 11: A read/write to ADDAR operates on the register within the extended register set
selected (pointed to) by the value in the address register. After that access is complete, for write
accesses only, the value in the address register is incremented. For read accesses, the value of the
address register remains unchanged.
8.2.1 Register Control Register (REGCR)
This register is the MDIO Manageable MMD access control. In general, register REGCR (4:0) is the
device address DEVAD that directs any accesses of the ADDAR (0x000E) register to the appropriate
MMD. REGCR also contains selection bits for auto increment of the data register. This register contains
the device address to be written to access the extended registers. Write 0x1F into bits 4:0 of this register.
REGCR also contains selection bits (15:14) for the address auto-increment mode of ADDAR.
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