TLK105 Datasheet, PDF (57/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
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SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
8.3 PHY Status Register (PHYSTS)
This register provides quick access to commonly accessed PHY control status and general information.
Table 8-18. PHY Status Register (PHYSTS), address 0x0010
BIT NAME
DEFAULT
DESCRIPTION
15 RESERVED 0, RO
RESERVED: Writes ignored, read as 0.
14 MDI-X Mode 0,RO
MDI-X mode as reported by the Auto-Negotiation state machine:
1 = MDI pairs swapped (Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal (Receive on TRD pair, Transmit on TPTD pair)
This bit will be affected by the settings of the AMDIX_EN and FORCE_MDIX bits in the PHYCR
register. When MDIX is enabled, but not forced, this bit will update dynamically as the Auto-MDIX
algorithm swaps between MDI and MDI-X configurations.
13 Receive Error 0,RO/LH Receive Error Latch:
Latch
1 = Receive error event has occurred since last read of RXERCNT register (0x0015)
0 = No receive error event has occurred
This bit will be cleared upon a read of the RECR register
12 Polarity Status 0,RO
Polarity Status:
1 = Inverted Polarity detected
0 = Correct Polarity detected
This bit is a duplication of bit 4 in the 10BTSCR register (0x001A). This bit will be cleared upon a read
of the 10BTSCR register, but not upon a read of the PHYSTS register.
11 False Carrier 0,RO/LH False Carrier Sense Latch:
Sense Latch
1 = False Carrier event has occurred since last read of FCSCR register (0x0014)
0 = No False Carrier event has occurred
This bit will be cleared upon a read of the FCSR register.
10 Signal Detect 0,RO/LL Signal Detect:
Active high 100Base-TX unconditional Signal Detect indication from PMD
9 Descrambler
Lock
0,RO/LL
Descrambler Lock:
Active high 100Base-TX Descrambler Lock indication from PMD
8 Page
Received
0,RO
Link Code Word Page Received:
1 = A new Link Code Word Page has been received. This bit is a duplicate of Page Received (bit 1)
in the ANER register and it is cleared on read of the ANER register (0x0006).
0 = Link Code Word Page has not been received.
This bit will not be cleared upon a read of the PHYSTS register.
7 MII Interrupt 0,RO
MII Interrupt Pending:
1 = Indicates that an internal interrupt is pending. Interrupt source can be determined by reading the
MISR Register (0x0012). Reading the MISR will clear this Interrupt bit indication.
0 = No interrupt pending
6 Remote Fault 0,RO
Remote Fault:
1 = Remote Fault condition detected. Fault criteria: notification from Link Partner of Remote Fault
via Auto-Negotiation. Cleared on read of BMSR register (0x0001) or by reset.
0 = No remote fault condition detected
5 Jabber Detect 0,RO
Jabber Detect:
1 = Jabber condition detected. This bit has meaning only in 10 Mb/s mode. This bit is a duplicate of
the Jabber Detect bit in the BMSR register (0x0001).
0 = No Jabber
This bit will not be cleared upon a read of the PHYSTS register.
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