TLK105 Datasheet, PDF (62/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
www.ti.com
Table 8-24. BIST Control Register (BISCR), address 0x0016 (continued)
BIT NAME
12 Packet Generation Enable
11 PRBS Checker Lock
10 PRBS Checker Sync Loss
9 Packet Gen Status
8 Power Mode
7 RESERVED
6 Transmit in MII Loopback
5 RESERVED
4:0 Loopback Mode
DEFAULT
0, RW
0,RO
0,RO,LH
0,RO
0,RO
0, RO
0, RW
0, RO
0, RW
DESCRIPTION
Packet Generation Enable:
1 = Enable packet generation with PRBS data
0 = Disable packet generator
PRBS Checker Lock Indication:
1 = PRBS checker is locked and synced on received bit stream
0 = PRBS checker is not locked
PRBS Checker Sync Loss Indication:
1 = PRBS checker lose sync on received bit stream – This is an error indication
0 = PRBS checker is not locked
Packet Generator Status Indication:
1 = Packet Generator is active and generate packets
0 = Packet Generator is off
Sleep Mode Indication:
1 = Indicate that the PHY is in normal power mode
0 = Indicate that the PHY is in one of the sleep modes, either active or passive
RESERVED: Writes ignored, read as 0.
Transmit Data in MII Loop-back Mode (valid only at 100BT):
1 = Enable transmission of the data from the MAC received on the TX pins to the
line in parallel to the MII loopback to RX pins. This bit may be set only in MII
Loopback mode – setting bit 14 in BMCR register (0x0000).
0 = Data is not transmitted to the line in MII loopback
RESERVED: Must be 0
Loop-back Mode Select:
The PHY provides several options for Loopback that test and verify various functional
blocks within the PHY. Enabling loopback mode allows in-circuit testing of the TLK10x
digital and analog data path
Near-end Loopback
00001 = PCS Input Loopback
00010 = PCS Output Loopback
00100 = Digital Loopback
01000 = Analog Loopback (requires 100Ω termination)
Far-end Loopback:
10000 = Reverse Loopback
8.10 RMII Control and Status Register (RCSR)
This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is
bypassed.
BIT NAME
15:6 RESERVED
5 RMII Mode
Table 8-25. RMII Control and Status Register (RCSR), address 0x0017
DEFAULT
<0000 0000
00>0,RO
0,RW, Pin_Strap
DESCRIPTION
RESERVED: Writes ignored, read as 0.
RMII Mode Enable:
1 = Enable RMII (Reduced MII) mode of operation
0 = Enable MII mode of operation
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Register Block
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