TLK105 Datasheet, PDF (13/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
www.ti.com
SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
3.9 Loopback Functionality
The TLK10x provides several options for Loopback that test and verify various functional blocks within the
PHY. Enabling loopback mode allows in-circuit testing of the TLK10x digital and analog data path.
Generally, the TLK10x may be configured to one of the Near-end loopback modes or to the Far-end
(reverse) loopback.
3.9.1 Near-End Loopback
Near-end loopback provides the ability to loop the transmitted data back to the receiver via the digital or
analog circuitry. The point at which the signal is looped back is selected using loopback control bits with
several options being provided. Figure 3-5 shows the PHY near-end loopback functionality.
MAC/
Switch
PCS Loopback
Analog Loopback
M
I
PCS
I
Signal
Process
PHY Digital
PHY
AFE
1
2
3
XFMR
4
5
6
7
8
MII Loopback
Digital Loopback
External Loopback
Figure 3-5. Block Diagram, Near-End Loopback Mode
The Near-end Loopback mode is selected by setting the respective bit in the BIST Control Register
(BISCR), MII register address 0x0016. MII loopback can be selected by using the BMCR register at
address 0x0000, bit [14].
The Near-end Loopback can be selected according to the following:
• Reg 0x0000, Bit [14]: MII Loopback
• Reg 0x0016, Bit [0]: PCS input Loopback
• Reg 0x0016, Bit [1]: PCS output Loopback
• Reg 0x0016, Bit [2]: Digital Loopback
• Reg 0x0016, Bit [3]: Analog Loopback
Table 3-4 describes the available operational modes for each loop mode:
Table 3-4. Loop Modes
Loop Mode
MII
PCS Input PCS Output
Operational Setting Force/ANEG 100/10 Force 100/10 Force 100
Operational MAC int.
MII Only
(1) Requires 100Ω termination
MII or RMII MII or RMII
Digital
Force 100
MII or RMII
Analog ⁽¹⁾
Force 10/100 ANEG
10
MII or RMII
External
Force/ANEG 100/10
MII or RMII
While in MII Loopback mode, there is no link indication, but packets propagate back to the MAC. While in
MII Loopback mode the data is looped back, and can also be transmitted onto the media. For transmitting
data during MII loopback in 100BT only please use bit [6] in the BISCR Register address 0x0016. To
ensure proper operation in Analog Loopback mode, 100Ω terminations should be attached to the RJ45
connector. External Loopback can be performed while working in normal mode (Bits 3:0 of the BISCR
register are asserted to 0, and on the RJ45 connector, pin 1 is connected to pin 3 and pin 2 is connected
to pin 6). To maintain the desired operating mode, Auto-Negotiation should be disabled before selecting
Loopback mode. This constraint is not relevant for external-loopback mode. For selected loopback Delay
propagation timing please see Section 9.6.21.
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Hardware Configuration
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