TLK105 Datasheet, PDF (65/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
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SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
Table 8-27. PHY Control Register (PHYCR), address 0x0019 (continued)
BIT NAME
5
LED CFG
DEFAULT
<0>, RW,
Pin_Strap
LED Configuration Modes:
DESCRIPTION
Mode
1
2
LED_CFG
1
0
LED_LINK
ON for Good Link
OFF for No Link
ON for Good Link
BLINK for Activity
4:0 PHY ADDR <0000 1>, RO PHY Address:
Strapping configuration for PHY Address.
8.13 10Base-T Status/Control Register (10BTSCR)
This register provides the ability to control and read status of the PHY’s internal 10Base-T functionality.
BIT
15:14
13
12:9
8
7
6:5
4
3:1
0
Table 8-28. 10Base-T Status/Control Register (10BTSCR), address 0x001A
NAME
DEFAULT
DESCRIPTION
RESERVED <000>, RO RESERVED: Writes ignored, read as 0.
Receiver TH 0,RW
Lower Receiver Threshold Enable:
1 = Enable 10Base-T lower receiver threshold to allow operation with longer cables
0 = Normal 10Base-T operation
Squelch
<0000>,RW
Squelch Configuration:
Used to set the Peak Squelch ‘ON’ threshold for the 10Base-T receiver. Every step is equal to
50mV and allow raising/lowering the Squelch threshold from 200mV to 600mV. The default
Squelch threshold is set to 200mV.
RESERVED 0, RO
RESERVED: Writes ignored, read as 0.
NLP Disable 0,RW
NLP Transmission Control:
1 = Disable transmission of NLPs
0 = Enable transmission of NLPs
RESERVED <00>, RO RESERVED: Writes ignored, read as 0.
Polarity Status 0,RO
10Mb Polarity Status:
1 = Inverted Polarity detected
0 = Correct Polarity detected
This bit is a duplication of bit 12 in the PHYSTS register (0x0010). Both bits will be cleared
upon a read of 10BTSCR register, but not upon a read of the PHYSTS register.
RESERVED <000>, RO RESERVED: Writes ignored, read as 0.
Jabber Disable 0,RW
Jabber Disable:
1 = Jabber function disabled
0 = Jabber function enabled
Note: This function is applicable only in 10Base-T
8.14 BIST Control and Status Register 1 (BICSR1)
This register provides the total number of error bytes that was received by the PRBS checker and defines
the Inter packet Gap (IPG) for the packet generator.
Table 8-29. BIST Control and Status Register 1 (BICSR1), address 0x001B
BIT BIT NAME
15:8 BIST Error
Count
DEFAULT
0, RO
DESCRIPTION
BIST Error Count:
Holds number of erroneous bytes that were received by the PRBS checker. Value in this
register is locked when write is done to bit[0] or bit[1] (see below).
When PRBS Count Mode set to zero, count stops on 0xFF. See BISCR register (0x0016) for
further details
Note: Writing “1” to bit 15 will lock counter’s value for successive read operation and clear the
BIST Error Counter.
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