TLK105 Datasheet, PDF (59/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
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SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
Table 8-19. PHY Specific Control Register (PHYSCR), address 0x0011 (continued)
BIT NAME
DEFAULT DESCRIPTION
11 Scrambler
Bypass
0,RW
Scrambler Bypass:
1 = Scrambler bypass enabled
0 = Scrambler bypass disabled
10 RESERVED 0, RO
RESERVED: Writes ignored, read as 0.
9:8 Loopback <01>,RW Far-End Loopback FIFO Depth:
FIFO Depth
00 = 4 nibbles FIFO
01 = 5 nibbles FIFO
10 = 6 nibbles FIFO
11 = 8 nibbles FIFO
This FIFO is used to adjust RX (recovered) clock rate to TX clock rate. FIFO depth need to be set
based on expected maximum packet size and clock accuracy. Default value sets to 5 nibbles.
7:5 RESERVED <000>,
RO
RESERVED: Writes ignored, read as 0.
4 COL FD
Enable
0, RW
Collision in Full-Duplex Mode:
1 = Enable generating Collision signaling in Full Duplex
0 = Disable Collision indication in Full Duplex mode. Collision will be active in Half Duplex only.
3 INT POL
1,RW
Interrupt Polarity:
1 = Steady state (normal operation) is 1 logic and during interrupt is 0 logic.
0 = Steady state (normal operation) is 0 logic and during interrupt is 1 logic.
2 tint
0,RW
Test Interrupt:
1 = Generate an interrupt
0 = Do not generate interrupt
Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will continue to be
generated as long as this bit remains set.
1 INT_EN
0,RW
Interrupt Enable:
1 = Enable event based interrupts
0 = Disable event based interrupts
Enable interrupt dependent on the event enables in the MISR register (0x0012).
0 INT_OE
0,RW
Interrupt Output Enable:
1 = INT / PWDN is an Interrupt Output
0 = INT / PWDN is a Power Down
Enable active low interrupt events via the INT / PWDN pin by configuring the INT / PWDN pin as an
output.
8.5 MII Interrupt Status Register 1 (MISR1)
This register contains events status and enables for the interrupt function. If an event has occurred since
the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the
register is set, an interrupt will be generated if the event occurs. The PHYSCR register (0x0011) bits 1 and
0 must also be set to allow interrupts. The status indications in this register will be set even if the interrupt
is not enabled.
Table 8-20. MII Interrupt Status Register 1 (MISR1), address 0x0012
BIT
15:14
13
NAME
RESERVED
Link Status Changed INT
12 Speed Changed INT
DEFAULT
<00>, RO
0,RO, COR
0,RO, COR
DESCRIPTION
RESERVED: Writes ignored, read as 0.
Change of Link Status interrupt:
1 = Change of link status interrupt is pending
0 = No change of link status
Change of Speed Status interrupt:
1 = Change of speed status interrupt is pending
0 = No change of speed status
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