TLK105 Datasheet, PDF (61/99 Pages) Texas Instruments – Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver

TLK105
TLK106
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SLLSEB8A – AUGUST 2012 – REVISED MARCH 2013
Table 8-21. MII Interrupt Status Register 2 (MISR2), address 0x0013 (continued)
BIT
NAME
5 Page Rec EN
4 Loopback FIFO OF/UF EN
3 MDI Crossover Changed EN
2 Sleep Mode Event EN
1 Polarity Changed EN
0 Jabber Detect EN
DEFAULT
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
DESCRIPTION
Enable Interrupt on page receive event
Enable Interrupt on loopback FIFO overflow/underflow event
Enable Interrupt on change of MDI/X status
Enable Interrupt sleep mode event
Enable Interrupt on change of polarity status
Enable Interrupt on Jabber detection event
8.7 False Carrier Sense Counter Register (FCSCR)
This counter provides information required to implement the "False Carriers" attribute within the MAU
managed object class of Clause 30 of the IEEE 802.3u specification.
Table 8-22. False Carrier Sense Counter Register (FCSCR), address 0x0014
BIT NAME
15:8 RESERVED
7:0 FCSCNT
DEFAULT DESCRIPTION
<0000 0000>, RO RESERVED: Writes ignored, read as 0
0,RO / COR
False Carrier Event Counter:
This 8-bit counter increments on every false carrier event. This counter stops when it
reaches its maximum count (FFh). When the counter exceeds half full (7Fh), an interrupt
event is generated. This register is cleared on read.
8.8 Receiver Error Counter Register (RECR)
This counter provides information required to implement the "Symbol Error During Carrier" attribute within
the PHY managed object class of Clause 30 of the IEEE 802.3u specification.
Table 8-23. Receiver Error Counter Register (RECR), address 0x0015
BIT
BIT NAME
15:0 RX Error Count
DEFAULT
DESCRIPTION
0, RO, / COR RX_ER Counter:
When a valid carrier is present (only while RXDV is set), and there is at least one occurrence of
an invalid data symbol, this 16-bit counter increments for each receive error detected. The
RX_ER counter does not count in MII loopback mode. The counter stops when it reaches its
maximum count of FFFFh. When the counter exceeds half-full (7FFFh), an interrupt is
generated. This register is cleared on read.
8.9 BIST Control Register (BISCR)
This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo
Random Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of
the exact loopback point in the signal chain is also done in this register.
Table 8-24. BIST Control Register (BISCR), address 0x0016
BIT NAME
15 RESERVED
14 PRBS Count Mode
13 Generate PRBS Packets
DEFAULT
0, RO
0, RW
0, RW
DESCRIPTION
RESERVED: Writes ignored, read as 0
PRBS Single/Continues Mode:
1 = Continuous mode, the PRBS counters reaches max count value, pulse is
generated and counter starts counting from zero again.
0 = Single mode, When BIST Error Counter reaches its max value, PRBS checker
stops counting.
Generated PRBS Packets:
1 = When packet generator is enabled, generate continuous packets with PRBS
data. When packet generator is disabled, PRBS checker is still enabled.
0 = When packet generator is enabled, generate single packet with constant data.
PRBS gen/check is disabled.
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