TLK100_11 Datasheet, PDF (8/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
www.ti.com
2.7 Jumper Options
Jumper option is an elegant way to configure the TLK100 into specific modes of operation. Some of the
functional pins are used as jumper options. The logic states of these pins are sampled during reset and
are used to configure the device into specific modes of operation. Below table shows the pins used for the
jumper option and its description. The functional pin name is indicated in parentheses.
A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default jumper option. If the default
option is required, then there is no need for external pull-up or pull down resistors. Since these pins may
have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND.
PIN
NAME
PHYAD0 (MII_COL)
PHYAD1 (MII_RXD_0)
PHYAD2 (MII_RXD_1)
PHYAD3 (MII_RXD_2)
PHYAD4 (MII_RXD_3)
TYPE
NO.
DESCRIPTION
24
25
26
27
28
S, O, PD
The TLK100 provides five PHY address pins, the states of which are latched into an
internal register at system hardware reset. The TLK100 supports PHY Address jumpering
values 0 (<00000>) through 31 (<11111>). All PHYAD[4:0] pins have weak internal
pull-down resistors.
AN_EN: When high, this puts the part into advertised Auto-Negotiation mode with the
capability set by AN_0 and AN_1 pins. When low, this puts the part into Forced Mode with
the capability set by AN_0 and AN_1 pins.
AN_0 / AN_1: These input pins control the forced or advertised operating mode of the
TLK100 according to the following table. The value on these pins is set by connecting the
input pins to GND (0) or VCC (1) through 2.2 kΩ resistors. These pins should NEVER be
connected directly to GND or VCC.
The status of these pins are latched into the Basic Mode Control Register and the
Auto_Negotiation Advertisement Register during Hardware-Reset.
The default is 111 since these pins have internal pull-ups.
AN_EN (LED_ACT)
AN_1 (LED_SPEED)
AN_0 (LED_LINK)
34
35 S, O, PU
36
AN_EN
0
0
0
0
AN_EN
1
1
1
1
AN_1
0
0
1
1
AN_1
0
0
1
1
AN_0
0
1
0
1
AN_0
0
1
0
1
Forced Mode
10BASE-T, Half-Duplex
10BASE-T, Full-Duplex
100BASE-TX, Half-Duplex
100BASE-TX, Full-Duplex
Advertised Mode
10BASE-T, Half/Full-Duplex
10BASE-TX, Half/Full-Duplex
10BASE-T, Half-Duplex
100BASE-TX, Half-Duplex
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
LED_CFG (MII_CRS)
This jumpering option along with LEDCR register bit determines the mode of operation of
22 S, O, PU the LED pins. Default is Mode 1. All modes are also configurable via register access. See
the table in the LED Interface Section.
MDIX_EN (MII_RX_ERR)
31
S, O, PU
This jumpering option sets the Auto-MDIX mode. By default it enables MDIX. An external
pull-down will disable Auto-MDIX mode.
8
Pin Descriptions
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