TLK100_11 Datasheet, PDF (35/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
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SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
6.4 Power Down Modes
TLK100 supports four types of power saving modes. The lowest power consumption is in the "Extreme
Low Power" mode (ELP). To enter into the ELP mode the PWRDNN/INT pin is pulled LOW.
To enable the power-down modes described below, set bit 11 of register BMCR (0x00h) to '1'. In all
power-down modes, the entire PHY is powered down except for the SMI interface; the PHY stays in that
condition as long as the value of bit 11 of register BMCR (0x00h) remains '1'. When this bit is cleared, the
PHY powers up and returns to the last state it was in before it was powered down.
In General Power Down mode, bits 9 and 8 of the PHYCR register (0x10h) should be set to "01".
Additionally, bit 4 of the PHYCR register (0x10h) should be set to '1' so as to power down the internal PLL.
The SMI would operate on the reference clock.
In Active sleep mode, or Energy-Detect mode, every 1.4 seconds a Normal Link Pulse (NLP) is sent to
wake up the link-partner. To enter into the active sleep mode, bits 9 and 8 of register PHYCR (0x10h) is
set to "10". Automatic powerup is done when the link partner is detected.
In passive sleep mode, all core blocks are powered down. Automatic power-up is done when the link
partner is detected. To enter into the passive sleep mode, bits 9 and 8 of register PHYCR (0x10h) is set to
"11".
Copyright © 2009, Texas Instruments Incorporated
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Reset and Power Down Operation
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