TLK100_11 Datasheet, PDF (61/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
www.ti.com
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
8.5.2 Cable Diagnostic Status Register (CDSR)
This register gives the status of the cable diagnostic tests. It also allows configuring different modes of the
ALCD and DSA tests.
Table 8-31. Cable Diagnostic Status Register (CDSR), address 0x001B
BIT
NAME
15 ALCD/DSA Done
14 TDR Fail
13 TDR Done
12:10 Reserved
9:6 DSA Input Signal
5 DSA Enable
4 ALCD/DSA mode
3:0 Reserved
DEFAULT
0,RO
1,RO
0,RO
0x4,RO
7,RW
0,RW
1,RW
0,RO
DESCRIPTION
1 = ALCD/DSA is done
0 = ALCD/DSA is not done
1 = TDR has failed
0 = TDR has not failed
1 = TDR is done
0 = TDR is not done
Ignore on read
7 = ALCD
5 = DSA Adaptive data mode
3 = DSA Raw data mode
Others are reserved
1 = DSA Engine is enabled
0 = DSA Engine is disabled
1 = DSA Raw data mode
0 = ALCD/DSA Adaptive data mode
Ignore on read
8.5.3 Cable Diagnostic Results Register (CDRR)
This register gives the result of the cable diagnostic tests. The software will post process this result.
Table 8-32. Cable Diagnostic Results Register (CDRR), address 0x001C
BIT
BIT NAME
15:0 Cable Diagnostics Result Register
DEFAULT
0, RO
DESCRIPTION
As specified in register 0x1A bits [11:8]
8.5.4 TDR State Machine Enable (TDRSMR)
This register allows configuration of the TDR state machines. Only when the bits 15, 14 of this register are
set to ‘1’ the registers 0x0090 and 0x0094 can be used.
Table 8-33. TDR State Machine Enable Register (TDRSMR), address 0x0080
BIT
NAME
15 cmn_tdr_sm_mode
14 cmn_tdr_tx_sm_m
ode
13:0 Reserved
TYPE
RW
RW
RW
RESET
0
0
0
FUNCTION
1 = Configure TDR state machine mode. This bit is cleared when TDR is complete
1 = Configure TDR transmit state machine mode. This bit is cleared when the TDR is
complete.
Reserved
Copyright © 2009, Texas Instruments Incorporated
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