TLK100_11 Datasheet, PDF (64/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
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8.5.12 TDR Low Threshold Register (TDRLT3)
This register allows configuring the threshold for finding the peaks of the reflected signal in the TDR test.
Table 8-41. TDR Low Threshold Register (TDRLT3), address 0x0C05
BIT
NAME
15 Reserved
14:8 cfg_ptrn_low_th_5
7
Reserved
6:0 cfg_ptrn_low_th_4
DEFAULT
0,RO
0x4,RW
0,RO
0x5,RW
FUNCTION
Ignore on read
Peak (absolute) low threshold value 5, for TX pattern.
Ignore on read
Peak (absolute) low threshold value 4, for TX pattern.
8.5.13 TDR Low Threshold Register (TDRLT4)
This register allows configuring the threshold for finding the peaks of the reflected signal in the TDR test.
Table 8-42. TDR Low Threshold Register (TDRLT4), address 0x0C06
BIT
NAME
15 Reserved
14:8 cfg_ptrn_low_th_7
7
Reserved
6:0 cfg_ptrn_low_th_6
DEFAULT
0,RO
0x3,RW
0,RO
0x3,RW
FUNCTION
Ignore on read
Peak (absolute) low threshold value 7, for TX pattern.
Ignore on read
Peak (absolute) low threshold value 6, for TX pattern.
8.5.14 TDR High Threshold Register (TDRHT1)
This register allows configuring the threshold for finding the peaks of the reflected signal in the TDR test.
Table 8-43. TDR High Threshold Register (TDRHT1), address 0x0C07
BIT
NAME
15 Reserved
14:8 cfg_ptrn_High_th_1
7
Reserved
6:0 cfg_ptrn_High_th_0
DEFAULT
0,RO
0x53,RW
0,RO
0x53,RW
FUNCTION
Ignore on read
Peak (absolute) High threshold value 1, for TX pattern.
Ignore on read
Peak (absolute) High threshold value 0, for TX pattern.
64
Register Block
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