TLK100_11 Datasheet, PDF (52/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
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8.2 Register Control Register (REGCR)
This register contains the device address to be written to access the extended registers. Write 0x1F into
bits 4:0 of this register. It also contains selection bits for auto increment of the data register.
BIT BIT NAME
15:1 Function
4
13:5 RESERVED
4:0 DEVAD
Table 8-12. Register Control Register (REGCR), address 0x000D
DEFAULT
0, RW
0, RO
0, RW
DESCRIPTION
00 = Address
01 = Data, no post increment
10 = Data, post increment on read and write
11 = Data, post increment on write only
RESERVED: Writes ignored, read as 0.
Device Address
8.3 Address or Data Register (ADDAR)
This is the address/data register.
BIT BIT NAME
15:0 Addr/data
Table 8-13. Data Register (ADDAR), address 0x000E
DEFAULT
0, RW
DESCRIPTION
If REGCR register 15:14 = 00, holds the MMD DEVAD's address register, otherwise holds the
MMD DEVAD's data register
52
Register Block
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