TLK100_11 Datasheet, PDF (5/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
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SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
2 Pin Descriptions
The TLK100 pins are classified into the following interface categories (each interface is described in the
sections that follow):
• Serial Management Interface
• MAC Data Interface
• Clock Interface
• LED Interface
• JTAG Interface
• Reset and Power Down
• Configuration (Jumper) Options
• 10/100 Mb/s PMD Interface
• Special Connect Pins
• Power and Ground pins
Note: Configuration pin option. See Section 2.7 for Jumper Definitions.
The definitions below define the functionality of each pin.
Type: I
Type: O
Type: I/O
Type: OD
Type: PD, PU
Type: S
Input
Output
Input/Output
Open Drain
Internal Pulldown/Pullup
Configuration Pin (All configuration pins have weak internal pullups or pulldowns. If
a different default value is needed, then use an external 2.2kΩ resistor. See
Section 2.7 for details.)
2.1 Serial Management Interface
PIN
NAME NO.
MDC
32
MDIO
33
TYPE
DESCRIPTION
MANAGEMENT DATA CLOCK: Clock signal for the management data input/output (MDIO) interface. The
I maximum MDC rate is 25 MHz; there is no minimum MDC rate. MDC is not required to be synchronous to the
MII_TX_CLK or the MII_RX_CLK.
I/O
MANAGEMENT DATA I/O: Bidirectional command / data signal synchronized to MDC. Either the local
controller or the TLK100 may drive the MDIO signal. This pin requires a pull-up resistor with value 1.5 kΩ.
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Pin Descriptions
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