TLK100_11 Datasheet, PDF (46/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
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8.1.3 PHY Identifier Register #1 (PHYIDR1)
BIT BIT NAME
15 OUI_MSB
Table 8-5. PHY Identifier Register #1 (PHYIDR1), address 0x0002
DEFAULT
<0010 0000 0000
0000>,
RO/P
DESCRIPTION
OUI Most Significant Bits: Bits 3 to 18 of the OUI (080028h) are stored in bits 15 to 0 of
this register. The most significant two bits of the OUI are ignored (the IEEE standard refers
to these as bits 1 and 2).
8.1.4 PHY Identifier Register #2 (PHYIDR2)
Table 8-6. PHY Identifier Register #2 (PHYIDR2), address 0x0003
BIT BIT NAME
15:10 OUI_LSB
9:4 VNDR_MDL
3:0 MDL_REV
DEFAULT
<101000>,
RO/P
<100000>,
RO/P
<0001>, RO/P
OUI Least Significant Bits:
DESCRIPTION
Bits 19 to 24 of the OUI (080028h) are mapped from bits 15 to 10 of this register respectively.
Vendor Model Number:
The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit 9).
Model Revision Number:
Four bits of the vendor model revision number are mapped from bits 3 to 0 (most significant bit to
bit 3). This field is incremented for all major device changes.
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Register Block
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