TLK100_11 Datasheet, PDF (34/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
www.ti.com
6 Reset and Power Down Operation
At power up it is recommended to have the external reset pin (RESETN) active (low). The RESETN pin
should be de-asserted 200μs after the power is ramped up to allow the internal circuits to settle and for
the internal regulators to be stabilized. If required during normal operation, the device can be reset by a
hardware or software reset.
6.1 Hardware Reset
A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1μs, to
the RESETN. This will reset the device such that all registers will be reinitialized to default values and the
hardware configuration values will be re-latched into the device (similar to the power-up/reset operation).
6.2 Software Reset
A software reset is accomplished by setting the reset bit (bit 15) of the BMCR register (0x00h). This bit
only resets the IEEE defined standard registers in the address space 0x00h to 0x07h. The software global
reset is accomplished by setting bit 15 of register PDN (0x001F) to ‘1’. This bit resets IEEE defined
registers (0x00h to 0x07h) and all the extended registers except for the cable-diagnostic registers and
RAM registers. For resetting the cable diagnostics and RAM registers, bit 14 of register RAMCR2
(0x0D01) should be set to ‘1’. The time from the point when the reset bit is set to the point the when
software reset has concluded is approximately 1.3 μs.
The software global reset resets the device such that all registers are reset to default values and the
hardware configuration values are maintained. Software driver code must wait 3 μs following a software
reset before allowing further serial MII operations with the TLK100.
6.3 Power Down/Interrupt
The Power Down and Interrupt functions are multiplexed on pin 42 of the device. By default, this pin
functions as a power down input and the interrupt function is disabled. This pin can be configured as an
interrupt output pin by setting bit 15 (INTN_OE) to ‘1’ and bit 12 (INTN_OEN) to ‘0’ of the MINTCR (0x14h)
register. Bit 13 of the same MINTCR register is used to set the polarity of the interrupt.
6.3.1 Power Down Control Mode
The PWRDNN/INT pin can be asserted low to put the device in a Power Down mode. An external control
signal can be used to drive the pin low, overcoming the weak internal pull-up resistor. Alternatively, the
device can be configured to initialize into a Power Down state by use of an external pulldown resistor on
the PWRDNN/INT pin.
6.3.2 Interrupt Mechanisms
The interrupt function is controlled via register access. All interrupt sources are disabled by default. The
MINTMR register provides independent interrupt enable bits for the different interrupts supported by
TLK100. The PWRDNN/INT pin is asynchronously asserted low when an interrupt condition occurs. The
source of the interrupt can be determined by reading the interrupt status register MINTSR (0x13h). One or
more bits in the MINTSR will be set, denoting all currently pending interrupts. Reading of the MINTSR
clears ALL pending interrupts.
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Reset and Power Down Operation
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