TLK100_11 Datasheet, PDF (36/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
7 Design Guidelines
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7.1 TPI Network Circuit
Figure 7-1 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. Below is a partial list
of recommended transformers. It is important that the user realize that variations with PCB and
component characteristics require that the application be tested to verify that the circuit meets the
requirements of the intended application.
• Pulse H1102
• Pulse HX1188
RD–
49.9 W
49.9 W
Vdd
Vdd
0.1 mF
Common-mode chokes
may be required.
1:1
RD–
RD+
0.1 mF*
RD+
TD–
49.9 W
49.9 W
TD+
Vdd
0.1 mF
TD–
0.1 mF*
1:1 ^T1
TD+
RJ45
Note: Center tap is connected to Vdd
* Place capacitors close to the
transformer center taps
Place resistors and capacitors close to the device.
All values are typical and are ±1%
S0339-01
Figure 7-1. 10/100 Mb/s Twisted Pair Interface
7.2 Clock In (XI) Requirements
The TLK100 supports an external CMOS-level oscillator source or an internal oscillator with an external
crystal.
7.2.1 Oscillator
If an external clock source is used, XI should be tied to the clock source and XO should be left floating.
The amplitude of the oscillator should be a nominal voltage of 1.8V.
36
Design Guidelines
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