TLK100_11 Datasheet, PDF (28/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
www.ti.com
5.1.3 NRZI and MLT-3 Encoding
To comply with the TP-PMD standard for 100BASE-TX transmission over CAT-5 unshielded twisted pair
cable, the scrambled data must be NRZI encoded. The serial binary data stream output from the NRZI
encoder is further encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level
represents a code bit '1' and the logic output remaining at the same level represents a code bit '0'.
5.1.4 Digital to Analog Converter
The multipurpose programmable transmit Digital to Analog Converter (DAC) receives digital coded
symbols and generates filtered analog symbols to be transmitted on the line. In 100B-TX the DAC applies
a low-pass shaping filter to minimize EMI. The DAC is designed to improve the return loss requirements
and enable the use of low-cost transformers.
Digital pulse-shape filtering is also applied in order to conform to the pulse masks defined by standard and
to reduce EMI and high frequency signal harmonics.
In 10Base-T, the Manchester coded symbols are fed through a pre-equalization filter.
5.2 Receive Path Decoder
In 10B-T, after the far end clock is recovered, the received Manchester symbols pass to the Manchester
decoder. The serial decoded bit stream is aligned to the start of the frame, de-serialized to 4-bit wide
nibbles and sent to the MAC through the MII.
In 100B-TX, the adaptive equalizer drives the received symbols to the MLT3 decoder. The decoded NRZ
symbols are transferred to the descrambler block for de-scrambling and de-serialization.
5.2.1 Analog Front End
The Receiver Analog Front End (AFE) resides in front of the 100B-TX receiver. It consists of an Analog to
Digital Converter (ADC), receive filters and a Programmable Gain Amplifier (PGA).
The ADC samples the input signal at the 125MHz clock recovered by the timing loop and feeds the data
into the adaptive equalizer. The ADC is designed to optimize the SNR performance at the receiver input
while utilizing high power-supply rejection ratio and maintaining low power. There is only one ADC in
TLK100, which receives the analog input data from the relevant cable pair, according to MDI-MDIX
resolution.
The PGA, digitally controlled by the adaptive equalizer, fully utilizes the dynamic range of the ADC by
adjusting the incoming-signal amplitude. Generally, the PGA attenuates short-cable strong signals and
amplifies long-cable weak signals.
5.2.2 Adaptive Equalizer
The adaptive equalizer removes Inter-Symbol Interference (ISI) from the received signal introduced by the
channel and analog Tx/Rx filters. The TLK100 includes both Feed Forward Equalization (FFE) and
Decision Feedback Equalization (DFE). The combination of the both adaptive modules with the adaptive
gain control results in a powerful equalizer that can eliminate ISI and compensate over the cable
attenuation for cables of up to 200m and even more. In addition, the Equalizer includes a Shift Gear Step
mechanism to provide fast convergence on the one hand and small residual-adaptive noise in Steady
state on the other hand.
5.2.3 Baseline Wander Correction
The DC offset of the transmitted signal is shifted down or up based on the polarity of the transmitted data
because the MLT-3 data is coupled onto the CAT 5 cable through a transformer that is high-pass in
nature. This phenomenon is called Baseline wander. To prevent corruption of the received data because
of this phenomenon, the receiver corrects the baseline wander and can receive the ANSI TP-PMD defined
"killer packet" with no bit errors.
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Architecture
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