TLK100_11 Datasheet, PDF (22/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
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4.2 Serial Management Interface
The Serial Management Interface (SMI), provides access to the TLK100’s internal registers space for
status information and configuration. The SMI is compatible with IEEE802.3-2002 clause 22. The
implemented register set consists of all the registers required by the IEEE802.3-2002 in addition to several
others, providing additional visibility and controllability of the TLK100 device.
The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock
is sourced by the external management entity (also referred to as STA), and can run at maximum clock
rate of 25MHz. MDC is not expected to be continuous, and can be turned off by the external management
entity when the bus is idle.
The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is
latched on the rising edge of the MDC clock. The MDIO pin requires a pull-up resistor (1.5kΩ) which,
during IDLE and turnaround, pulls MDIO high.
Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used.
During power-up reset, the TLK100 latches the PHYAD[4:0] configuration pins (Pin 25 to Pin 28) to
determine its address.
The management entity must not start an SMI transaction in the first cycle after power-up reset.
To maintain legal operation, SMI bus should remain inactive at least one MDC cycle after hard reset is
de-asserted.
In normal MDIO transactions, the register address is taken directly from the management frame’s
reg_addr field, thus allowing direct access to 32 16-bit registers (including those defined in IEEE802.3
and vendor specific). The data field is used for both reading and writing.
The Start code is indicated by a <01> pattern. This makes sure that the MDIO line transitions from the
default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address
field and the Data field. To avoid contention during a read transaction, no device may actively drive the
MDIO signal during the first bit of Turnaround. The addressed TLK100 drives the MDIO with a zero for the
second bit of turnaround and follows this with the required data. Figure 4-2 shows the timing relationship
between MDC and the MDIO as driven/received by the Station (STA) and the TLK100 (PHY) for a typical
register read access.
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