TLK100_11 Datasheet, PDF (55/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
www.ti.com
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
8.4.3 MII Interrupt Mask Register (MINTMR)
This register contains enables for various interrupt functions supported by TLK100.
Table 8-16. MII Interrupt Mask Register (MINTMR), address 0x0012
BIT
NAME
15 Auto-Negotiation Interrupt Enable
14 Speed Changed Interrupt Enable
13 Duplex Mode Changed Interrupt
Enable
12 Page Received Interrupt Enable
11 Auto-Negotiation Completed Interrupt
Enable
10 Link Status Changed Interrupt Enable
9:8 Reserved
7 FIFO Overflow/Underflow Interrupt
Enable
6 MDI Crossover Changed Interrupt
Enable
5 Reserved
4 Sleep Mode Changed Interrupt
Enable
3:2 Reserved
1 Polarity Changed Interrupt Enable
0 Jabber Interrupt Enable
DEFAULT
0, RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RO
0,RW
0,RW
0,RO
0,RW
0,RO
0,RW
0,RW
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
Ignore on read
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
Ignore on read
1 = Enable interrupt
0 = Disable interrupt
Ignore on read
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
DESCRIPTION
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Register Block
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