TLK100_11 Datasheet, PDF (6/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
2.2 MAC Data Interface
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PIN
NAME
MII_TX_CLK
MII_TX_EN
MII_TXD_0
MII_TXD_1
MII_TXD_2
MII_TXD_3
MII_RX_CLK
MII_RX_DV
MII_RX_ERR/MDIX_EN
MII_RXD_0/PHYAD1
MII_RXD_1/PHYAD2
MII_RXD_2/PHYAD3
MII_RXD_3/PHYAD4
MII_CRS/LED_CFG
MII_COL/PHYAD0
TYPE
NO.
DESCRIPTION
19
O, PD
MII TRANSMIT CLOCK: : MII Transmit Clock provides 25MHz or 2.5MHz reference
clock depending on the speed.
MII TRANSMIT ENABLE: MII_TX_EN is presented on the rising edge of the
18
I, PD MII_TX_CLK . It indicates the presence of valid data inputs on MII_TXD[3:0]. It is an
active high signal.
13
14
15
IS, I, PD
MII TRANSMIT DATA: The transmit data nibble received from the MAC that is
synchronous to the rising edge of the MII_TX_CLK.
16
23
O
MII RECEIVE CLOCK: MII receive clock provides a 25MHz or 2.5MHz reference clock,
depending on the speed, that is derived from the received data stream.
30
S, O, PD
MII RECEIVE DATA VALID: This pin indicates valid data is present on the
corresponding MII_RXD[3:0].
31
S, O, PU
MII RECEIVE ERROR: This pin indicates that an error symbol has been detected within
a received packet.
25
26
27
28
MII RECEIVE DATA: Symbols received on the cable are decoded and presented on
S, O, PD these pins synchronous to MII_RX_CLK. They contain valid data when MII_RX_DV is
asserted.
22 S, O, PU MII CARRIER SENSE: This pin is asserted high when the receive medium is non-idle.
MII COLLISION DETECT: In Full Duplex Mode this pin is always low. In
24 S, O, PU 10BASE-T/100BASE-TX half-duplex modes, this pin is asserted HIGH only when both
the transmit and receive media are non-idle.
2.3 Clock Interface
PIN
TYPE
NAME
NO.
DESCRIPTION
CRYSTAL/OSCILLATOR INPUT: Reference clock. 25MHz ±50 ppm tolerance crystal reference or
XI
39
I oscillator input. The TLK100 supports either an external crystal resonator connected across pins XI and
XO, or an external CMOS-level oscillator source connected to pin XI only.
XO
37
O
CRYSTAL OUTPUT: Reference Clock output. XO pin is used for crystal only. This pin should be left
floating when an oscillator input is connected to XI.
CLK25OUT
12
25 MHz CLOCK OUTPUT: In MII mode, this pin provides a 25 MHz clock output to the system. This
O allows other devices to use the reference clock from the TLK100 without requiring additional clock
sources.
2.4 LED Interface
(See Table 3-3 for LED Mode Selection)
PIN
NAME
NO.
LED_LINK/AN_0
36
LED_SPEED/AN_1 35
LED_ACT/AN_EN 34
TYPE
DESCRIPTION
S, O, PU
S, O, PU
S, O, PU
This pin indicates the status of the link in Mode 1. When the link is good the LED will be ON. In
Mode 2 and Mode 3, this pin indicates transmit and receive activity in addition to the status of the
Link. The LED is ON when Link is good. It will blink when the transmitter or receiver is active.
This pin indicates the speed of the link. It is ON when the link speed is 100 Mb/s and OFF when it
is 10 Mb/s.
In mode 1 this pin indicates if there is any activity on the link. It is ON (pulse) when activity is
present on either Transmit or Receive channel. In Mode 3, this LED output may be programmed to
indicate Full-duplex status.
6
Pin Descriptions
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