TLK100_11 Datasheet, PDF (29/88 Pages) Texas Instruments – Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

TLK100
www.ti.com
SLLS931B – AUGUST 2009 – REVISED DECEMBER 2009
5.2.4 NRZI and MMLT-3 Decoding
The TLK100 decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI
data. The NRZI-to-NRZ decoder is used to present NRZ-formatted data to the descrambler.
5.2.5 Descrambler
The descrambler is used to descramble the received NRZ data. It is further deserialized and the
parallelized data is aligned to 5-bit code-groups and mapped into 4-bit nibbles. At initialization, the
100B-TX descrambler uses the IDLE-symbols sequence to lock on the far-end scrambler state. During
that time, neither data transmission nor reception is enabled. After the far-end scrambler state is
recovered, the descrambler constantly monitors the data and checks whether it still synchronized. If, for
any reason, synchronization is lost, the descrambler tries to re-acquire synchronization using the IDLE
symbols.
5.2.6 45/5B Decoder
The code-group decoder functions as a look up table that translates incoming 5-bit code-groups into 4-bit
nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and
replaces the J/K with a MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the
nibble pair (0101 0101). All subsequent 5-bit code-groups are converted to the corresponding 4-bit nibbles
for the duration of the entire packet. This conversion ceases upon the detection of the T/R code-group pair
denoting the End-of-Stream Delimiter (ESD), or on the reception of a minimum of two IDLE code-groups.
5.2.7 Timing Loop and Clock Recovery
The receiver must lock on the far-end transmitter clock in order to sample the data at the optimum timing.
The timing loop recovers the far-end clock frequency and offset from the received data samples and
tracks instantaneous phase drifts caused by timing jitter.
The TLK100 has a robust adaptive-timing loop (Tloop) mechanism that is responsible for tracking the
Far-End TX clock and adjusting the AFE sampling point to the incoming signal. The Tloop implements an
advanced tracking mechanism that when combined with different available phases, always keeps track of
the optimized sampling point for the data, and thus offers a robust RX path to both PPM and Jitter. The
TLK100 is capable of dealing with PPM and jitter at levels far higher than those defined by the standard.
5.2.8 Phase-Locked Loops (PLL)
In 10B-T the digital phase lock loop (DPLL) function recovers the far-end link-partner clock from the
received Manchester signal The DPLL is able to combat clock jittering of up to ±18ns and frequency drifts
of ±500ppm between the local PHY clock and the far-end clock. The DPLL feeds the decoder with a
decoded serial bit stream.
The integrated analog Phase-Locked Loop (PLL) provides the clocks to the analog and digital sections of
the PHY. The PLL is driven by an external reference clock (sourced at the XI,XO pins).
5.2.9 Link Monitor
The TLK100 implements the link monitor SM as defined by the IEEE 802.3 100BASE-TX Standard. In
addition, the TLK100 enables several add-ons to the link monitor State Machine(SM) activated by
configuration bits. These add-ons are supplementary to the IEEE standard and are enabled by default.
The new add-ons include the recovery state which enables the PHY to attempt recovery in the event of a
temporary energy loss situation or link failure before entering LINK_FAIL state, and thus, restarting the
whole link establishment procedure. This allows significant reduction of the recovery time if the temporary
link is lost.
To move to the LINK_DOWN state, the link monitor state machine relies on various criteria such as
descrambler synchronization failure, SNR, and energy indications. These criteria allow the TLK100 to
reach the fast link down time mode when required.
Copyright © 2009, Texas Instruments Incorporated
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